Posted by on September 11, 19103 at 02:15:09:
G Krishnamurthy
3440 Warburton Avenue, Unit 7 Santa Clara CA 95051 gxk172@yahoo.com; 408-319-0261
Summary Bringing in over five years of rich programming & functional experience in both software and hardware industry.
Education
July ‘93- B.S in Electrical Engineering
July ‘97 Indian Institute of Technology, (IIT) Madras, India
Aug ’99- M.S in Electrical Engineering
Dec ‘00 Penn State University, University Park, PA
Skills Verilog/VHDL, Mentor Graphics, PERL, Synopsys, C,C++,ABAP/4,PL/SQL, HTML 4.0 and XML,
Experience Beyond Innovations
Jan ’03-present System Analyst - SAP Integration
Technical Expertise:
SAP ABAP/4, SAP Script, SAP Business Workflow, SAP- Legacy System Integration using BAPI.
ABAP Expertise:
User defined Reports and Interfaces as per requirements.
Batch Input Programs, Sequential Files, calling Transactions from within ABAP/4 Reports
Report Writing - Lists and Dialog Oriented Report Programming.
Conversion and Interface
Module pool & Transactions Development including screen & menu painter
Developed ABAP/4 Reports
SAP Enhancements & User Exits.
SAP Data Dictionary (Tables, Data Elements, Domain, Match Code Objects and Views).
Jan ‘01- Sun Microsystems
Dec ’02 Member of Technical Staff 2, UltraSPARC Microprocessor Division
• Design and Verification of Cluster Blocks within the ULTRA SPARC Microprocessors Chip.
• Physical Design Verification (PDV), using Calibre, of Megacells to run back-end flow (Design Rule Check [DRC], Electric Rules Checks [ERC], Layout VS Schematic [LVS]).
• Simulation and evaluation of power, area and timing in adder critical path in the low-power CMOS Arithmetic and Logic unit
• Back-annotation, post-layout RC extraction and timing analysis of semi-custom digital blocks
• Estimation and checking metal migration effects in layout
• Characterization of semi-custom blocks for functionality, timing, noise, metal density, Physical design verification, functional equivalency check
• Analysis, simulation and testing of clock topology for clock skew, rise and fall time on cluster blocks
• Analysis and simulation of on-chip noise effects in clusters
Aug ‘99- CEDCC, Penn State University and Marconi Communications
Dec ’00 MS Graduate student, Research Assistant and summer intern
• Modification of VHDL test Bench for Packet Over SONET (POS) to implement loop back mechanism of Level-3 specification by PMC-SIERRA
• Synthesis of VHDL RTL in Xilinx FPGA, simulation, floor-planning, place-route, back-annotation in the design and development of smart-memory architecture to reduce the processor-memory gap (www.cedcc.psu.edu/smartdimm)
• Design and layout of the smart-memory board that plugs on the memory DIMM slot
• Studying and evaluating Firewire (IEEE 1394), USB, PCI, AGP bus and also memory buses PC100, PC133 and RAMBUS DDRAM, and recommending the most appropriate bus technology to implement the smart-memory design.
• Diagnosis, simulation, testing and bringing-up OC-48 Network modules and boards and rewriting test-benches in VHDL
• Description in single cycle of MIPS Microprocessor using VHDL
• Programming in C for neural network topology
• Design of four Combinational logic block (CLB) FPGA and layout design at polygon level for the circuit, and testing and simulation of the circuit
• Design of different types of filters in Digital Signal Processing course
• Analysis, study and simulation of Cache coherency protocol (MESI) in a snooping bus architecture and testing the cache hierarchy
Aug ’97- Telco, India
July ’99 Software engineer – SAP implementation
Key Responsibilities:
• ABAP/4 Programmer and Functional Consultant implemented in MM and SD.
• Functioned as an Electronic Data Interchange (EDI) on legacy/EDI to SAP/EDI conversion.
• Worked in gap analysis, mapping of transaction to EDI subsystem, defining partner profile, port definition, condition tables for output determination. Transaction included 810,844,850,855 and 856.
• EDI Responsibilities included the initial mapping of the transaction inbound and outbound with ANSIX12.
• Receiving and sending of Partner transaction through VAN.
• Worked with IDocs and several trading Partner Profiles for Inventory, Warehouse Management, Orders, Sales support and Shipping.
Aug’ 94- Microprocessor Research Lab, IIT Madras, India
July ’97 Research Assistant
• Writing Games software for industries in C
• Writing Assembly Language code for Motorola Microcontrollers for implementing varied digital circuits