Posted by on September 11, 19103 at 02:12:05:
Gourishankar Krishnamurthy
3450 Warburton Avenue, #7 Santa Clara CA 95051 USA; gourishpk@yahoo.com; 408-319-0261
Summary Bringing in over five years of industrial experience in analog and mixed-signal design, with a MSEE from Penn State and BSEE from IIT Madras, India and interested in applying my analog design skills in a dynamic team
Relevant
Skills
• FPGA design using Synopsys-Synplify, Xilinx design Manager and Cadence Programmable IC flow
• Schematic design entry using Cadence Concept HDL
• VHDL RTL design and functional verification using Cadence tools and verilog-XL simulator
• Transistor-level layout design & simulation using Micromagic(0.25u), IRSIM and HSPICE
• Low-power design using Powermill
• Static timing analysis using Pathmill
• Design and functional equivalency check using Chrysalis
• Physical design verification (drc, erc, lvs) using Calibre-PDV
• Writing scripts for diagnosis and verification using PERL
Industry
Experience Beyond Innovations
01/03-present Sr. ASIC design Engineer Consultant
• Analysis, simulation and testing of clock topology for clock skew, rise and fall time on cluster blocks
• Analysis and simulation of on-chip noise effects in clusters
• Design and simulation of video compression ICs, MPEG 2-4 for graphics chip design project effort
01/01-12/02 Sun Microsystems
Member of Technical Staff 2, UltraSPARC Microprocessor Division
• Leading 3-4 mask layout designers in supervising the design effort of semi-custom digital blocks
• Simulation and evaluation of power, area and timing in adder critical path in the low-power CMOS Arithmetic and Logic unit
• Back-annotation, post-layout RC extraction and timing analysis of semi-custom digital blocks
• Estimation and checking metal migration effects in layout
• Characterization of semi-custom blocks for functionality, timing, noise, metal density, Physical design verification, functional equivalency check
08/99-12/00 Center for Electronic Design, Communication & Computing (CEDCC) and Marconi Communications
Electronics Engineer
• Study of USB, IEEE1394 Firewire, PCI and AGP bus technology and peripheral-interface
• Design of four Combinational logic block (CLB) FPGA and layout design at polygon level for the circuit, and testing and simulation of the circuit
• Testing of Network Modules and ATM switches that support OC-48 Packet over SDH/SONET (POS), MPLS over PPP and one-armed router functionality
• Writing diagnostic scripts (pragmas) for FPGA registers in the Network Module
• Modified the test-bench for the loop-back mechanism to implement UTOPIA/POS-PHY Level 3 specification by PMC-SIERRA
• Analysis, study and simulation of Cache coherency protocol (MESI) in a snooping bus architecture and testing the cache hierarchy
• Synthesis of VHDL RTL in Xilinx FPGA, simulation, floor-planning, place-route, back-annotation in the design and development of smart-memory to reduce the processor-memory gap (www.cedcc.psu.edu/smartdimm)
• Design and layout of the smart-memory board that plugs on the memory DIMM slot
• Design of different types of filters-low-pass, band-pass and band-stop
8/97-7/99 Telco, India
ASIC design Engineer (for automotive applications)
• Leading 10 people in commissioning of Nachi and Ogata Robots, programming ladder logic diagrams for Allen Bradley PLC and Panel View and Human-Machine Interface Diagnostic messages and control, Cabling of signals, designing RS-232 and RS-484 interface.
• Writing and debugging Assembly Language code for Intel 8051 Micro-controller-based digital clock and selecting the LCD display from different vendors.
• Designing SGS-Thompson Micro-controller based Glow-Plug Timer for improving the fuel efficiency of Diesel Engine based SUV;
• Designing the PCB layout in PCAD for Light Delay Unit used for internal Lighting in cars
• Design specification, commissioning and wiring of Allen Bradley PLC panels, programming the PLC, designing Graphics User Interface (GUI) for motor control, lighting, camera control and automatic-monitoring of vehicle crash test center using RS-View 32