Posted by on September 11, 19103 at 02:08:57:
Gourishankar Krishnamurthy
3440 Warburton Avenue, Unit 7 Santa Clara CA 95051 gourishpk@yahoo.com; 408-319-0261
Summary Bringing in over five years of digital firmware design, micro-controller programming, ASIC/VLSI design and hardware-software interface and apply skills to a dynamic team
Education
07/93- 07.97 B.S in Electrical Engineering
Indian Institute of Technology, (IIT) Madras, India
08/99-12/00 M.S in Electrical Engineering
Penn State University, University Park, PA
Skills Cadence, Hspice, Powermill, PathMill, Simplex, Chrysalis, Calibre, FPGA
&Tools design (Xilinx and Altera), Verilog/VHDL, Mentor Graphics, PERL, Synopsys, C, Assembly Language
Experience
01/03-present Beyond Innovations, Inc.
Electric Engineer
• Responsible for the design and development of Portables BIOS and Firmware platforms and docking stations
01/01-12/02 Sun Microsystems
Member of Technical Staff 2, UltraSPARC Microprocessor Division
• Design and develop the micro-controllers for controlling the motion of printers and interfacing with the processors.
• Simulation and evaluation of power, area and timing in adder critical path in the low-power CMOS Arithmetic and Logic unit
• Back-annotation, post-layout RC extraction and timing analysis of semi-custom digital blocks
• Estimation and checking metal migration effects in layout
• Characterization of semi-custom blocks for functionality, timing, noise, metal density, Physical design verification, functional equivalency check
• Analysis, simulation and testing of clock topology for clock skew, rise and fall time on cluster blocks
• Analysis and simulation of on-chip noise effects in clusters
08/99-12/00 CEDCC, Penn State University and Marconi Communications
MS Graduate student, Research Assistant and summer intern
• Synthesis of VHDL RTL in Xilinx FPGA, simulation, floor-planning, place-route, back-annotation in the design and development of smart-memory architecture to reduce the processor-memory gap (www.cedcc.psu.edu/smartdimm)
• Design and layout of the smart-memory board that plugs on the memory DIMM slot
• Studying and evaluating Firewire (IEEE 1394), USB, PCI, AGP bus and also memory buses PC100, PC133 and RAMBUS DDRAM, and recommending the most appropriate bus technology to implement the smart-memory design.
• Diagnosis, simulation, testing and bringing-up OC-48 Network modules and boards and rewriting test-benches in VHDL
• Description in single cycle of MIPS Microprocessor using VHDL
• Programming in C for neural network topology
• Design of four Combinational logic block (CLB) FPGA and layout design at polygon level for the circuit, and testing and simulation of the circuit
• Design of different types of filters in Digital Signal Processing course
07/97-07/99 Telco, India
Electrical Engineer
• Leading 10 people in commissioning of Nachi and Ogata Robots, programming ladder logic diagrams for Allen Bradley PLC and Panel View and Human-Machine Interface Diagnostic messages and control, Cabling of signals, designing RS-232 and RS-484 interface.
• Writing and debugging Assembly Language code for Intel 8051 Micro-controller-based digital clock and selecting the LCD display from different vendors.
• Designing SGS-Thompson Micro-controller based Glow-Plug Timer for improving the fuel efficiency of Diesel Engine based SUV;
• Designing the PCB layout in PCAD for Light Delay Unit used for internal Lighting in cars
• Design specification, commissioning and wiring of Allen Bradley PLC panels, programming the PLC, designing Graphics User Interface (GUI) for motor control, lighting, camera control and automatic-monitoring of vehicle crash test center using RS-View 32
07/94-07/97 Microprocessor Research Lab, IIT Madras, India
Research Assistant
• Writing Games software for industries in C
• Writing Assembly Language code for Motorola Microcontrollers for implementing varied digital circuits