Posted by on September 11, 19103 at 02:07:59:
Gourishankar Krishnamurthy
3440 Warburton Avenue, Unit 7 Santa Clara CA 95051 gourishpk@yahoo.com; 408-319-0261
Summary Bringing in over five years of digital ASIC design and DFT experience and aspiring to be a part of a dynamic team working on ASIC/CMOS VLSI design, simulation, DFT, physical design verification
Education
July ‘93- B.S in Electrical Engineering
July ‘97 Indian Institute of Technology, (IIT) Madras, India
Aug ’99- M.S in Electrical Engineering
Dec ‘00 Penn State University, University Park, PA
Skills Cadence, ATPG, BIST, NC-Verilog, Hspice, Powermill, PathMill, Simplex,
&Tools Chrysalis, Calibre, FPGA design (Xilinx and Altera), Verilog/VHDL, Mentor Graphics, PERL, Synopsys (design Compiler, Synplify, Prime-time), C, Assembly Language
Experience Beyond Innovations
Jan ’03-present DFT Engineer
• Participate in the architectural DFT planning and evaluation
• Implement DFT schemes, like scan, BIST and JTAG
• Integrate commercial ATPG tool to design flow and generate
high quality test patterns
• Perform Iddq and delay fault testing
Jan ‘01- Sun Microsystems
Dec ’02 Member of Technical Staff 2, UltraSPARC Microprocessor Division
• Define and implement thorough Global SRAM testing methodology
Work with Design Verification Team to generate functional test
vectors
• Generate appropriate verilog test vectors for characterization, debugging
and failure analysis of clusters in UltraSPARC Microprocessor
• Understand the logic design and develop methodologies to test
the various blocks, including driving partitioning, targeted
stimulus generation, simulation and vector extraction, conversion
and debug on the tester.
• Take ownership of the system to tester correlation problem from
the vector generation perspective and rewrite/simulate system tests
and extract vectors for the test coverage improvement
• Leading 3-4 mask layout designers in supervising the design effort of semi-custom digital blocks
• Design and Verification of Cluster Blocks within the ULTRA SPARC Microprocessors Chip.
• Physical Design Verification (PDV), using Calibre, of Megacells to run back-end flow (Design Rule Check [DRC], Electric Rules Checks [ERC], Layout VS Schematic [LVS]).
• Simulation and evaluation of power, area and timing in adder critical path in the low-power CMOS Arithmetic and Logic unit
• Back-annotation, post-layout RC extraction and timing analysis of semi-custom digital blocks
• Estimation and checking metal migration effects in layout
• Characterization of semi-custom blocks for functionality, timing, noise, metal density, Physical design verification, functional equivalency check
• Analysis, simulation and testing of clock topology for clock skew, rise and fall time on cluster blocks
• Analysis and simulation of on-chip noise effects in clusters
Aug ‘99- CEDCC, Penn State University and Marconi Communications
Dec ’00 MS Graduate student, Research Assistant and summer intern
• Modification of VHDL test Bench for Packet over SONET (POS) to implement loop back mechanism of Level-3 specification by PMC-SIERRA
• Synthesis of VHDL RTL in Xilinx FPGA, DFT simulation, floor-planning, place-route, back-annotation in the design and development of smart-memory architecture to reduce the processor-memory gap (www.cedcc.psu.edu/smartdimm)
• Design, DFT and layout of the smart-memory board that plugs on the memory DIMM slot
• Studying and evaluating Firewire (IEEE 1394), USB, PCI, AGP bus and also memory buses PC100, PC133 and RAMBUS DDRAM, and recommending the most appropriate bus technology to implement the smart-memory design.
• Diagnosis, simulation, testing and bringing-up OC-48 Network modules and boards and rewriting test-benches in VHDL
• Description in single cycle of MIPS Microprocessor using VHDL
• Programming in C for neural network topology
• Design, DFT of four Combinational logic block (CLB) FPGA and layout design at polygon level for the circuit, and testing and simulation of the circuit
• Design of different types of filters in Digital Signal Processing course
• Analysis, study and simulation of Cache coherency protocol (MESI) in a snooping bus architecture and testing the cache hierarchy
Aug ’97- Telco, India
July ’99 Electrical Engineer
• Leading 10 people in commissioning of Nachi and Ogata Robots, programming ladder logic diagrams for Allen Bradley PLC and Panel View and Human-Machine Interface Diagnostic messages and control, Cabling of signals, designing RS-232 and RS-484 interface.
• Writing and debugging Assembly Language code for Intel 8051 Micro-controller-based digital clock and selecting the LCD display from different vendors.
• Designing SGS-Thompson Micro-controller based Glow-Plug Timer for improving the fuel efficiency of Diesel Engine based SUV;
• Designing the PCB layout in PCAD for Light Delay Unit used for internal Lighting in cars
• Design specification, commissioning and wiring of Allen Bradley PLC panels, programming the PLC, designing Graphics User Interface (GUI) for motor control, lighting, camera control and automatic-monitoring of vehicle crash test center using RS-View 32
Aug’ 94- Microprocessor Research Lab, IIT Madras, India
July ’97 Research Assistant
• Writing Games software for industries in C
• Writing Assembly Language code for Motorola Microcontrollers for implementing varied digital circuits