Posted by on August 18, 19103 at 14:22:45:
Hello,
My name is Prakash Patil and I am seeking a VLSI design engineering position and am enclosing my resume for your kind consideration. I holds M.Tech. (Microelectronic) from IIT. My most recent experience is with VLSI working on back-end physical design.
Kind Regards,
Prakash Patil
My Resume is as
Prakash Patil
PL5B-1/15, Sector 10, Khanda Colony,
New Panvel, Navi Mumbai-410206, INDIA
patilph@yahoo.com
patilph@lycos.com
prakash.patil@indiatimes.com
http://hightech.4jobs.com/PRAKASHHPATIL
Cell Phone:0091-22-32754844.
Phone:0091-22-27457267.
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OBJECTIVE: Expertise in physical VLSI Design.
EXPERIENCE SUMMARY: One & half years of experience in physical design of Integrated Circuit (IC). Good skills and experience of deep sub micron IO pad library design, verification, design of test chip, ESD & Latch-up issues, Failure analysis. Good communication skills. Excellent leadership qualities.
SKILLS
ASIC / VLSI Physical Design Expert Currently used 2 years.
Software Proficiency: Cadence Tool, Mentor Graphics caliber tool,
SKILL script, HP Unix, Win NT, C programming, C++.
EXPERIENCE: 3/2001 to 8/2002 - Philips Semiconductors, The Netherlands, Standard Cell Design Engineer.
Major role in Shrink CMOS18 micron & CMOS12 micron IO pad library Design. Computer aided physical design of CMOS12 & CMOS18 micron library design, verification. Verification & merging of new cells to Standard cell library & maintenance.
SHRINK CMOS18 library physical design, verification: Verification of new cells, merging of new cells & maintenance of complete SHRINK CMOS18 IO pad library. Complete SHRINK CMOS18 micron IO pad library converted from CMOS 18 IO pad library. All the IO pad layouts of SHRINK 18 micron standard cell library converted from cmos18 library for SHRINK process. It itself is a big project. New Physical design Layout like level shifter, PCI, P1394, USB, PECL, SSTL etc.
A role in the silicon qualification (electrical, ESD and Latch-up issues) of the I/O libraries. Design of test chips for IO pads of standard cell library and participation in the testing and failure analysis. Besides the general-purpose input, output and bi-directional cells, the current libraries contain new cells developed according industrial standards (SSTL-2, PCI, USB, PECL, etc.).
* Software used: Cadence complete Backend Qualified Design flow (QDF 3.1), Skill scripts, and Calibre Mentor Graphics tool.
* O.S. platform used: WinNT, HP-Unix.
* Team Size:4.
* Training Undergone: Cadence Qualified Design flow (QDF 3.1): Three & half day of extensive training on complete front end & backend design flow.
SKILL language : SKILL language for Cadence design tool. Extensive five days of training.
EDUCATION: 3/2000 Indian Institute Of Technology Bombay, Mumbai,India.
Master of Technology in Microelectronic (M.Tech.) with GPA 6.85 out of 10.
Some of the courses studied at M.Tech. are as:
VLSI Design, VLSI Technology, Computer Aided Analysis and Design, System Hardware Design, Physical Electronics, Modern Electronic Design Techniques, MOS Devices, Special Semiconductor Devices, Microelectronic Lab.
Projects at M.Tech:
1) Study of Multi-layer Multi-chip Architecture. (Carried out at I. I. T. Bombay during year 1998-2000)
Project consists of Design & development of IC interconnects of multi-layer multi-chip architectures. The Elmore delay model is widely used in optimizing the wire sizing area of an interconnect. The wire sizing algorithms such as Optimal Wire Sizing under Elmore Delay, Greedy Wire Sizing Algorithm under the Elmore Delay and Extended Wire Sizing Algorithm under the Elmore Delay considered for the design of an interconnects in the circuit of multi-layer multi-chip architectures. The optimal wire sizing solution satisfies a number of interesting properties such as seperability, monotone and dominance properties. These properties considered at time of design of an interconnects. These algorithms are implemented to get the fruitful results. The code is written in `C' language. The results received are the delay required for the signal from source node to the destination node (e.g. driver node to the sink node in the circuit). The time complexity is calculated. User-friendly software developed for complete analysis and design of the interconnects in the circuit.
11/1990 Cusrow Wadia Institute of Technology, Pune India.
Advanced Diploma course in Computer software system Analysis & Applications. It is one & half year program.
7/1988 Shivaji University Kolhapur, India; Batchler of Engineering in Electronics.
AREAS OF INTEREST:
ASIC Design.
VLSI Design.
VLSI Fabrication.
VLSI verification & Testing.
Personal Information.
Marital Status Married
Nationality Indian
Passport Id A9784706
Children One