Posted by on July 22, 19103 at 01:34:34:
CURRICULUM VITAE
VARSHA GUPTA
Flat-A1, Venketshwar Complex . E-mail: gupta_varsha28@hotmail.com
Jain Temple Road, Konanagrahara gupta_varsha28@yahoo.com
Murgesh Palaya, HAL Post Office, Tel: 080 5227343
Bangalore - 560017 Mobile No: 09844007320
OBJECTIVE
Seeking a challenging career, which gives me the opportunities to prove my
expertise in the field of Digital Electronics and VLSI. I am a team player
and hence I would like to share and enhance my knowledge in the process.
EXPERTISE
HARDWARE
Hardware Description Languages: VHDL, VERILOG
Script Language: TCL/TK.
Assembly Languages: 8085, 8086.
Simulator Tools: ModelSim EE 5.4b, ModelSim Altera Version 5.4e,
ModelSim Actel 5.5.
Synthesizer Tools: Exempler Leonardo spectrum Version 2.0, Synplify
Backend Tools: Xilinx Alliance Series 2.1 for place and routing,
ACTEL -Designer Series
Tools : Altera Quartus II,The “QUARTUS II software” integrates
Design, synthesis, place & route and verification in to a
seamless environment including interfaces to third party
EDA tools.
SOFTWARE
Languages: C, C++, Visual C++, and DATA STRUCTURE IN C.
Operating Systems: WINDOWS 9X/NT/2000, MS-DOS, UNIX
WORK EXPERIENCE
2 years 10 months of experience in VLSI Front-End Design, FPGA designing ,
VHDL coding , simulation, synthesis, timing verification and testing .
1 year experience in Lectureships .
1. Working with, Dexcel Electronics Designs (P) Ltd, Bangalore as “Member Technical Staff“
from 5th July, 2001- till date.
2. Pursuing VLSI Training ,from 5th Feb. to 15th June 2001 from C-DAC(Centre for Development
of Advanced Computing), Hyderabad
3. Worked as “Design Engineer “ in Dexcel Electronics Designs (P) Ltd ,Bangalore from
19th Sep. 2000 to 25th Jan 2001.
4. Worked as Lecturer in Govt. Engineering College, Raipur, from Sep. 1999 to Sep 2000 ,
where my major responsibility was to teach and guide the students and also included
managing , planning and making strategies to meet the day to day targets and needs.
PROJECTS EXECUTED
1. RLDRAM Controller IP Core
· Duration: March 2003 to July 2003
· Tools: Altera Quartus II, Model Sim, Leonardo Spectrum
· Team Size: 2
· Client: Altera
· Position: Project Member
· Role: Architecture to RTL level Designing, VHDL coding, Functional
verification (script driven testbenches), Logical synthesis , Timing
verification , fusing FPGA
· Brief Description:
o The RLDRAM Controller designed to control three RLDRAMs (Micron) for line card
application. The Controller Interfaces with RLDRAM at 120 MHz , double data rate
(240 Mbps ) and fusing in to Altera stratix (1S30F1020C6) device .
It supports Burst length 2, Read and write latencies of according to 200 MHz
configuration option 4 , data write masking , autorefreshing .
2. FPGA design for the development of a Generic cardbus to PCI Bridge
· Duration: Dec. 2002 to Feb 2003
· Tools: Altera Quartus II, Model Sim, Leonardo Spectrum
· Team Size: 4
· Client: Philips
· Position: Project Member
· Role: VHDL coding, Functional verification, timing verification , fusing
FPGA
· Brief Description:
o The designed FPGA act as a bridge for interfacing PCI card with the Cardbus .
It supports any standard 32 bit, 33 M. Hz. PCI devices adhere to PCI 2.1/2.2
standards. In this design the total solution is seen as a single Cardbus Card.
3. E1 Framer
· Duration: 6 months
· Tools: Altera Quartus II, Model Sim, Leonardo Spectrum
· Team Size: 3
· Client: Dexcel
· Position: Project Member
· Role: Architecture to RTL level Designing, VHDL coding, Functional
verification (script driven testbenches), Logical synthesis , Timing
verification , fusing FPGA
· Brief Description:
o E1 framer based on ITU-T standard G.704, G. 706, and G.732 specifications.
E1 Framer frames serial data to E1 streams and the de-framer portion extracts
the serial data out from an E1 framed stream. The design also included a
microprocessor (Intel/ Motorola) interface . The target device used is Altera
Apex 20KE400. Maximum frequency of operation of the design is 2.048 MHz.
The device utilization around 28k gates.
4. TDES (Triple DES) IP Core
· Duration: 1 month
· Tools: Altera Quartus II, Model Sim, Leonardo Spectrum
· Team Size: 2
· Client: Dexcel
· Position: Project Member
· Role: Architecture to RTL level Designing, VHDL coding, Functional
verification (script driven testbenches), Logical synthesis , Timing
verification , fusing FPGA
· Brief Description:
o TDES Design core implementation based on FIPS 46-3 . This IP core is fully.
synchronous design which supports both encryption and decryption.The target
device used is Altera’s APEX EPK200EFC484-1 , fmax-80Mhz .
The Design is optimized for low gate count.
5. I2C Interface Controller
· Duration: 2 month
· Tools: Altera Quartus II, Model Sim, Leonardo Spectrum
· Team Size: 2
· Client: Dexcel
· Position: Project Member
· Role: Architecture to RTL level Designing, VHDL coding, Functional
verification (script driven testbenches), Logical synthesis , Timing
verification , fusing FPGA
· Brief Description:
o I2C Bus Controller logic provides a serial interface that meets the Philips
I2C bus specification and supports 7-bit Addressing , standard transfer mode
(up to 100 kbit/s) and Fast Mode (up to 400 kbit/s) from and to the I2C bus .
The I2C Interface Controller design contains a Microprocessor (Intel/ Motorola)
interface and provides I2C Master/Slave capability.
6. IP Core for RTP & RTCP Engine
· Duration: 4 month
· Tools: Altera Quartus II, Model Sim, Leonardo Spectrum
· Team Size: 2
· Client: Dexcel
· Position: Project Member
· Role: Architecture to RTL level Designing, VHDL coding, Functional
verification (script driven testbenches), Logical synthesis , Timing
verification , fusing FPGA
· Brief Description:
o RTP & RTCP Engine IP core Fully compliant to RFC 1889/1890 .
RTP is the Internet-standard protocol for the transport of real-time data,
including audio and video . RTP consists of a data (RTP) and a control part
(RTCP) . Design Supports more than one channel, belonging to the same RTP
Session.
CONVERSANT WITH TECHNOLOGIES
· Familiar with different Interfaces like I2C, Parallel Port, RS 232
· Familiar with NIOS embedded processor.
· CSIX –L1 (Common Switch Interface Specification)
· ITU-T Standard G.704, G.706, and G.732 specifications
· IETF RFC 1889/1890 (RTP and RTCP)
· FIPS 46-3 (DES standard)
· UART , SDH, HDB3/AMI encoding and decoding .
ACADEMIC PROJECTS
· Flash Memory (ATMEL AT49BV001N flash memory) controller IP core
· E1 Framer Transmitter and Receiver (as major project in C-DAC)
· Simulation of 8255 (as mini project in C-DAC)
· SPEECH RECOGNITION USING FUZZY LOGIC
· SWITCH MODE POWER SUPPLY
ACADEMIC PROFILE
· Post Graduate Diploma in VLSI, (from 5th Feb. to 15th June 2001) from CDAC
(Centre for Development of Advanced Computing), Hyderabad with 68.2% (B+ grade).
· Bachelor of Engineering in Electronics Engineering, 1999, from Govt. Engineering
College, Raipur, Pt. Ravishankar University with aggregate of 77.4% (Hons.).
· Diploma in Electronics & Telecommunication Engg. 1995, from Govt. Women’s
Polytechnic, Raipur with aggregate of 76.2% (Hons.).
· Higher Secondary School, 1993, from M.P.Board of Education, Bhopal with 78.4%.
· High School, 1991 from M.P.Board of Education, Bhopal with 76%.
PERSONAL PROFILE
Father Name: Dr. L. N. GUPTA
Date of Birth: 28-06-1975
Nationality: Indian
Permanent Address: 478, Priya Darshini Nagar,
Near saint Dyaneshwar school,
Ring road 1, Raipur (Chhatisgarh),
India, 492001
Martial Status: Single
Hobbies: Writing poetries & classical dance (Kathak)
Languages known: Hindi, English
REFERENCES
1. Mr. Suman Basu
Software Design Engg.
(ASIC Product Development Center)
Texas Instruments ,Bangalore .
Tel : 91-80-5099596
Mobile No: 9845124457
2. Mr. M. R. Khan
HOD, Dept. of Electronics & Communication,
Govt. Engineering College, Raipur (Chhatisgarh)
3. NANJUNDASWAMY H.R
Senior design engineer and ex-lecturer
Dexcel Designs Electronics Ltd.,bangalore
Varsha Gupta