Posted by on July 21, 19103 at 06:35:41:
PANDI THURAI.S
Room No.57, Suganthi Complex, E-mail: pandiaec@yahoo.com
# 30, Rameswaram Road,
T.Nagar, Chennai-17. Phone: 044- 24314116 Extn:157
Mobile no: 09840345470.
Objective:
To become a challenging professional where I can put forth my efforts for the organizational efficiencies.
Work Experience:
VLSI Design Engineer having 2+ years of experience in Verilog HDL, VHDL, IP design, SoC integration. Well trained in full software cycle activities.
Working at Accel Software and Technologies Ltd., Chennai - 29, India.
Technical Skills:
Digital Design methodologies and FSM based system design.
VHDL,Verilog HDL based RTL design and synthesis methodology.
8-bit Processor architecture (8085).
8-bit controller architecture (8051).
FPGA synthesis and back annotation.
ASIC Design Methodologies.
Knowledge in Static Timing Analysis.
Timing simulation.
Knowledge in ARM architecture.
Knowledge in Analog Circuits.
Quality process and Documentation.
EDA Tools Handled:
Cadence Verilog - XL Simulator.
Modelsim Simulator for Verilog HDL and VHDL.
Cadence AMBIT synthesizer.
Xilinx foundation series.
Leonardo spectrum synthesizer
Educational Profile:
B.E from University of Madras with 74% June 1996 to June 2000.
Current project:
· SDRAM controller.
Duration : 5 months
Team members : 4
EDA tools : Modelsim ,Xilinx foundation series.
HDL : VHDL
Abstract : The SDRAM controller is designed for transferring the data between any Industry Standard SDRAMs. It interfaces the SDRAM memory subsystem with a 32-bit generic host interface. It performs SDRAM read and write access based on the host requests. The SDRAM controller is fully programmable. All access timings are fully programmable to support different speed grades of SDRAM devices and different operating frequencies.
Responsibility:
Involved in low level Architecture Design and Documentation.
VHDL coding and functional verification for Refresh controller and Host interface modules.
Synthesis and Timing simulation.
Guidance for team mate for developing functional and error test cases for low level and high level modules.
Skills Acquired:
Design Documentation.
Intel i960 Cx/Hx series 32-bit microprocessor system bus operation.
SDRAM memory standards.
FSM based system design development.
VHDL RTL coding and test bench development.
Projects Handled :
BFM Model for AMBA(SoC Standard):
Duration : 6 months
Team members : 4
EDA tools : Modelsim PE Simulator.
Xilinx foundation series.
HDL : VHDL
Abstract : AMBA BFM models the behaviour of an AMBA AHB master, slave, arbiter and decoder. AMBA AHB BFM creates a typical integrated verification environment in which an AMBA AHB master, slave, arbiter and decoder are integrated together. Depending upon the inputs through the user interface the BFM will initiate transactions and thus creating traffic on the bus.
Responsibility:
Involved in High level and low level Architecture Design and Documentation.
VHDL coding and functional verification for Master and slave module.
Integrated test plan preparation.
Skills Acquired:
Design Documentation.
FSM based reusable system design development.
VHDL coding and test bench development.
RTL Model for Programmable Peripheral Interface (PPI):
Duration : 4 months
EDA tools : Leonardo spectrum.
Modelsim.
HDL : VHDL
Abstract : The PPI is programmable peripheral interface, which programmed by the 8-bit host to communicate with parallel Input/output devices. It acts as interface between parallel host and device. It can be programmed to transfer data, from simple I/O to interrupt I/O and three different modes of operation. The PPI core is functionally compatible to PPI 8255A from Intel.
Responsibility:
Involved in low level Architecture Design and Documentation.
VHDL coding and functional verification for Low level modules.
Skills Acquired:
Design Documentation.
FSM based system design development.
VHDL RTL coding and test bench development.
Leonardo spectrum and modelsim.
RTL Model for Programmable Interval Timer (PIT):
Duration : 4 months
EDA tools : Leonardo spectrum.
Modelsim.
HDL : Verilog
Abstract : The PIT is programmable Interval Timer, which programmed by the 8-bit host for incorporating the hardware delays. The PIT core is functionally compatible to PIT 8254A from Intel. The model was developed with following features
1) Six modes of operation.
2) Read back command.
3) Counter latch command.
Responsibility:
Involved in low level Architecture Design and Documentation.
Verilog HDL coding and functional verification for Low level modules.
Skills Acquired:
Design Documentation.
FSM based system design development.
Verilog HDL RTL coding and test bench development.
Leonardo spectrum and modelsim.
RTL Model for USART:
Duration : 4 months
Team members : 3
EDA tools : Cadence Verilog - XL Simulator.
Modelsim PE Simulator.
HDL : Verilog
Abstract : The USART is peripheral device, which programmed by the 8-bit host to communicate with serial data transmission device. It acts as interface between parallel host and serial device. The USART accepts the data characters from the host in the parallel format and then converts them into a continuous serial data stream for transmission. Simultaneously, it can receive serial data streams and convert them into parallel character for host. It can be programmed for synchronous or asynchronous mode of operation. The USART core is functionally compatible to USART 8251A from Intel.
Responsibility:
Involved in Low level Architecture Design and Documentation.
Verilog HDL coding and functional verification for Transmitter module.
Skills Acquired:
Design Documentation.
FSM based system design development.
Verilog HDL RTL coding and test bench development.
Leonardo spectrum and modelsim.
Curriculum Project:
DIGITAL PID CONTROLLER USING RISC PIC 16C84 MICROCONTROLLER:
Abstract:
This project is to develop a high speed, low cost and easily programmable digital controller, to be used in closed loop control systems. The digital PID Controller consists of PIC16C84 as CPU, which performs digital PID action on digital error signal and generates digital control signals.