Posted by on July 16, 19103 at 01:39:59:
CURRICULUM VITAE
VARSHA GUPTA
Flat-A1, Venketshwar Complex . E-mail: gupta_varsha28@hotmail.com
Jain Temple Road, Konanagrahara gupta_varsha28@yahoo.com
Murgesh Palaya, HAL Post Office, Tel: 080 5227343
Bangalore - 560017 Mobile No: 09844007320
OBJECTIVE
To seek a challenging career and growth oriented position in field of VLSI. Looking for a friendly environment and teamwork where my knowledge and experience can be shared and enriched.
SKILL SETS
SOFTWARE
Languages: C, C++, Visual C++, and DATA STRUCTURE IN C.
Operating Systems: WINDOWS 9X/NT/2000, MS-DOS, UNIX
HARDWARE
Assembly Languages: 8085, 8086.
Hardware Description Languages: VHDL, VERILOG (PURSUING from CDAC).
Simulator Tools: ModelSim EE 5.4b, ModelSim Altera Version 5.4e, ModelSim Actel 5.5.
Synthesizer Tools: Exempler Leonardo spectrum Version 2.0, Synplify
Backend Tools: Xilinx Alliance Series 2.1 for place and routing, Quartus II, The “QUARTUS II software” integrates Design, synthesis, place & route and verification in to a seamless environment including interfaces to third party EDA tools. ACTEL -Designer Series
Script Language: TCL/TK .
EXPERIENCE
1. Working with, Dexcel Electronics Designs (P) Ltd, Bangalore as “Member Technical Staff “ from 5th July, 2001- till date. 2 years of experience in the VLSI front-end design, digital field Design of digital circuits for FPGAs using schematic entry, VHDL coding , simulation, synthesis, timing verification and board level design and testing.
2. Worked as Lecturer in Govt. Engineering College, Raipur, from 9/9/99 to 25/01/2001, where my major responsibility was to teach and guide the students in lab and also to work out strategies for achieving the regular target assigned to me.
PROJECTS HANDLED
1. RLDRAM Controller
· Duration: 3rd March 2003 to till date
· Tools: Altera Quartus II, Model Sim, Leonardo Spectrum
· Team Size: 2
· Client: Altera
· Position: Project Member
· Role: Designing, VHDL coding, Functional simulation, timing simulation, fusing FPGA
· Operating system: Windows 2000
· Language: VHDL
· Brief Description:
o The Micron or Infineon 256Mb Reduced Latency DRAM (RLDRAM) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) format where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.
o The Reduced Latency Dynamic Random Access Memory (RLDRAM) Controller provides a 200 MHz double data rate physical interface to the Micron Technology or Infineon Technologies 16 bit wide RLDRAM’s.
2. FPGA design for the development of a Generic cardbus to PCI Bridge
· Duration: Dec. 2002 to Feb 2003
· Tools: Altera Quartus II, Model Sim, Leonardo Spectrum
· Team Size: 4
· Client: Philips
· Position: Project Member
· Role: VHDL coding, Functional simulation, timing simulation, fusing FPGA
· Operating System: Windows 2000
· Language: VHDL
· Brief Description:
o This design is a FPGA based bridging solution for interfacing PCI card with the Cardbus. It supports any standard 32 bit, 33 M. Hz. PCI devices adhere to PCI 2.1/2.2 standards. In this design the total solution is seen as a single Cardbus Card.
3. E1 Framer
· Duration: 6 months
· Tools: Altera Quartus II, Model Sim, Leonardo Spectrum
· Team Size: 3
· Client: Dexcel
· Position: Project Member
· Role: Designing, VHDL coding, Functional simulation, timing simulation, fusing FPGA
· Operating System: Windows 2000
· Language: VHDL
· Brief Description:
o E1 framer based on ITU-T standard G.704, G. 706, and G.732 specifications.
o E1 Framer frames serial data to E1 streams and the de-framer portion extracts the serial data out from an E1 framed stream. Other than the framer / de-framer logic, the design included a microprocessor interface. The target device used is Altera’s Apex 20KE400. Maximum frequency of operation of the design is 2.048 MHz. It consumes around 28k gates.
4. TDES (Triple DES) IP Core
· Duration: 1 month
· Tools: Altera Quartus II, Model Sim, Leonardo Spectrum
· Team Size: 2
· Client: Dexcel
· Position: Project Member
· Role: Designing, VHDL coding, Functional simulation, timing simulation, fusing FPGA
· Operating System: Windows 2000
· Language: VHDL
· Brief Description:
o Implementation based on FIPS 46-3. The Data Encryption Standard (DES) algorithm is a block cipher that transforms 64-bit data blocks under a 64-bit secret key, by means of permutation and substitution. It is officially described in FIPS PUB 46. A new encryption algorithm, Triple DES was proposed as an alternate to DES.
5. IP Core for RTP & RTCP Engine
· Duration: 4 month
· Tools: Altera Quartus II, Model Sim, Leonardo Spectrum
· Team Size: 2
· Client: Dexcel
· Position: Project Member
· Role: Designing, VHDL coding, Functional simulation, timing simulation, fusing FPGA
· Operating System: Windows 2000
· Language: VHDL
· Brief Description:
o RTP is the Internet-standard protocol proposed by IETF for the transport of real-time data, including audio and video. It can be used for media-on-demand as well as interactive services such as Internet telephony. RTP consists of a data and a control part. The latter is called RTCP. RTP and RTCP engine implementation based on RFC.1889/1890.
6. I2C Interface Controller
· Duration: 2 month
· Tools: Altera Quartus II, Model Sim, Leonardo Spectrum
· Team Size: 2
· Client: Dexcel
· Position: Project Member
· Role: Designing, VHDL coding, Functional simulation, timing simulation, fusing FPGA
· Operating System: Windows 2000
· Language: VHDL
· Brief Description:
o Philips developed a simple bi-directional 2-wire bus for efficient inter-IC Control. The I2C bus is a two-wire interface, with serial transfer, is used in many systems because of its low overhead. Two bus lines are required; a Serial Data Line (SDA) and a Serial Clock Line (SCL). Each device connected to the bus is software addressable by a unique address and simple master/slave relationships. It’s a true multi-master bus including collision detection and data transfers can be made at up to 100 kbit/s in the Standard Mode, up to 400 kbit/s in the Fast Mode or up to 3.4 Mbit/s in the High-speed Mode. The I2C Interface Controller design contains a Microprocessor (Intel/ Motorola) interface and provides I2C Master/Slave capability.
ACADEMIC PROJECTS
· E1 Framer Transmitter and Receiver (as major project in C-DAC)
· Simulation of 8255 (as mini project in C-DAC)
· SPEECH RECOGNITION USING FUZZY LOGIC
· SWITCH MODE POWER SUPPLY
AWARENESS OF TECHNOLOGIES
· Familiar with different Interfaces like I2C, Parallel Port, RS 232
· Familiar with NIOS embedded processor.
· CSIX –L1 (Common Switch Interface Specification)
· ITU-T Standard G.704, G.706, and G.732 specifications
· IETF RFC 1889/1890
· FIPS 46-3
ACADEMIC PROFILE
· Diploma in VLSI, (from 5th Feb. to 15th June 2001) from C-DAC (Centre for Development of Advanced Computing), Hyderabad with 68.2% (b+ grade).
· Bachelor of Engineering in Electronics Engineering, 1999, from Govt. Engineering College, Raipur, Pt. Ravishankar University with aggregate of 77.4% (Hons.).
· Diploma in Electronics & Telecommunication Engg. 1995, from Govt. Women’s Polytechnic, Raipur with aggregate of 76.2% (Hons.).
· Higher Secondary School, 1993, from M.P.Board of Education, Bhopal with 78.4%.
· High School, 1991 from M.P.Board of Education, Bhopal with 76%.
PERSONAL PROFILE
Father Name: Dr. L. N. GUPTA
Date of Birth: 28-06-1975
Nationality: Indian
Permanent Address:
478, Priya Darshini Nagar,
Near saint Dyaneshwar school,
Ring road 1, Raipur (Chhatisgarh),
India, 492001
Martial Status: Single
Hobbies: Writing poetries & classical dance (Kathak)
Languages known: Hindi, English
References:
1. Mr. M. R. Khan
HOD, Dept. of Electronics & Communication,
Govt. Engineering College, Raipur (Chhatisgarh)
2. NANJUNDASWAMY H.R
Senior design engineer and ex-lecturer
Dexcel Designs Electronics Ltd.,bangalore
Varsha Gupta