Posted by on June 26, 19103 at 17:32:03:
Dear employers,
Joining a dynamic company through Taiwan Online.com
I would like to join a good job through Taiwan Online.com, as a new Hardware Design Engineer and bringing to the organization my 5+ years of experience working on Sun Microsystems, CEDCC, Marconi Communications and TELCO.
My training at TELCO helped me become Hardware Design Engineer. After my Masters at Pennsylvania State University and my experience working at CEDCC, I improved my Engineering skills for Design Engineering, which helped me provide good working background in Sun Microsystems.
Many of these skills apply to job Position especially which needs skills in ASIC, VLSI, CMOS, FPGS, PLC positions etc.
I'd be happy to discuss these ideas at an interview.
Yours sincerely
Gourish
Curriculum Vitae of Gourishankar Krishnamurthy
120 Cornell dr SE Albuquerque New Mexico 87106
Email: gourishpk@yahoo.com Cell: (408) 319-0261
OBJECTIVE:
Bringing in over five years of digital ASIC design experience and being a part of a dynamic team working on ASIC/VLSI design, simulation, DFT, physical design verification
SUMMARY OF MAJOR EXPERIENCE:
· 1.5 years in CEDCC, USA working as an ASIC/VLSI design Engineer
· 2 years in TELCO, India working as Electrical Engineer designing and Commissioning Digital circuits and control panels
· 2 years in Sun Microsystems, USA, working in the UltraSPARC Design Division as a CMOS circuit design Engineer
· 3 months on summer intern at Marconi Communication, Pittsburgh, USA working in bringing up boards and rewriting test-benches in VHDL
EDUCATION:
· B.S in Electrical Engineering 07/93-07/97
Indian Institute of Technology, Chennai (IIT Madras) India
· M.S in Electrical Engineering 07/99-12/00
Penn State University, University Park, PA
· PhD in Computer Engineering 05/03-present
University of New Mexico, Albuquerque, NM
SKILLS SUMMARY:
Personal Skills:
Successfully lead and managed a team of 10 strong technical people under various projects initiatives. Posses excellent Written and Verbal communication skills. Met many Project deadlines using Organizational and Interpersonal skills.
CMOS VLSI circuit design: Cadence Virtuoso for Schematic Editor (opus schematic editor), Hspice for functional and timing simulation, Powermill for Power measurements and estimation, PathMill for timing analysis, EM-tool for checking Electro-migration limits, Simplex for Static EM, IR and Signal EM, Chrysalis for formal verification, Calibre for Physical Design Verification (PDV) flow for drc, lvs, schematic and layout erc, noise-tool for noise analysis
ASIC/ Logic design: Xilinx top-down design tools for FPGA design, Altera Max-Plus-II for CPLD design, Verilog-XL for functional simulation and test-benches, Cadence Design Analyzer, and Modelsim
Board design: Cadence Allegro PCB Layout, PCAD for PCB design, 8051 Microcontroller design.
Programming and Operating Systems: VERILOG, VHDL, PERL, UNIX, Windows
EXPERIENCE DETAILS:
High Performance Computing Center
Research Assistant, Albuquerque, NM 05/03 -- present
Working in SMP architecture on the High Performance Computing Laboratory
Sun Microsystems, Sunnyvale, CA
Member of Technical Staff, Hardware 01/01-- 12/02
Worked on ASIC/VLSI design in the multiple full custom, low power very high-speed digital blocks in the next generation UltraSPARC microprocessor family with 8 Metal Layers at the Sun Microelectronics Division
Design of Integer execution unit (IEU) and Arithmetic and logic unit (ALU) data path and evaluation of power, area and delay of two different adders and design, simulation, functionality, critical path analysis in Integer Execution Unit
Accomplishments:
Completed RTL design, synthesis and HSPICE simulation and CMOS design of static adder with low threshold voltage evaluation and also using dynamic adder and comparing the results and presentation of IEU data path comparison of the two different style of implementation
Design and characterization of mega-cells
Accomplishments:
Completed characterizing a mega cell ‘pipctl’, which is the valid and dispatch block. This involved working in the mega-cell team and RTL and circuit specification, schematic design capture, transistor-level and static gate-level timing analysis, simulation using HSPICE, EM/IR flow using Simplex, noise analysis using noise-tool, checking rtl vs. schematics for equivalence using Chrysalis, working with mask designers, block place and route, physical verification (lvs, drc, erc) using Calibre, holding reviews and documenting work, and final delivery of the mega-cell.
Design and development of Perl-based script for verifying Electro-migration limits
Accomplishments:
Designed a running script for checking EM limits for metal layers, vias and contacts.
Ran the clock-flow in mega cells, clusters, and blocks in the Microprocessor. Running at transistor level, this tool was used to test the different hierarchies in the Microprocessor for clock skew for different levels of clock routing.
Accomplishments:
Helped the clock team in running valuable test routines to check at the clock skew numbers and was critical to the tape-out of the Microprocessor
Tools used At Sun Microsystems:
Calibre for Physical Design Verification (PDV) flow, Hspice, Powermill, PathMill, EMtool, Simplex for Static EM, IR and Signal EM, PERL for scripting, Verilog-XL, Cadence Design Analyzer, Chrysalis, mkgmv
Center for Electronic Design, Communication and Computing (CEDCC), PA
Part-time Research and Development Engineer 07/99 – 04/00 and 09/00-12/00
Embedded systems design, development and testing
Working in Smart memory architecture (processor with embedded memory design), selecting dual ported Scrams and regular Scrams for image processing applications
Accomplishment:
Studying I/O and peripheral buses IEEE1394, USB, Firewire, IDE, PCI bus, PCI express and AGP and memory buses PC100, Presentation of the bus study and recommendations of the appropriate bus architecture for smart-memory applications in Image processing of MPEG/JPEG, FPGA accelerators, and Network Interface Applications, programming on-board Xilinx FPGA & RISC Processor, selection of on-board memory, coding RTL, synthesis using Synplify, Place and Route using Programmable IC (PIC) flow, design, verification, and back-annotation of design, VISIO documentation. (WEB SITE: http://www.cedcc.psu.edu/smartdimm); this involved improving the processor memory speed from a standard PCI interface bandwidth to PC10
Tools used at CEDCC:
Synopsys/Synplify, Cadence, Altera CPLD and Xilinx Programmable IC (PIC) flow for top-down design, Modelsim, VHDL, Allegro, and HP Oscilloscope 0 access
Marconi Communications, Warrendale, PA
Summer intern 05/00-08/00
Powering up an OC-48 Network Module and testing the board for clock skews, signal integrity, slew rates, etc
Accomplishment:
Successfully powered up 5 network modules, and programmed the boot-code in the Xilinx virtex FPGA
Modifying the VHDL test bench of a loop-back mechanism used in OC-48 rate Network Module
Accomplishment:
Running MODELSIM simulation tests, and conclusion resulting in the modification and demonstrating loop-back feature
Designing Xilinx Virtex FPGA based Network Modules and writing pragmas for diagnostic scripts for programs running in Xilinx Virtex based FPGA to be used in OC-48 rate Network Modules
Accomplishment:
RTL design of the core, synthesis, timing verification, Place and Route, Back-Annotation and verification of the design.
Tools used at Marconi Communications:
Modelsim, VHDL, Allegro, and HP Oscilloscope
Tata Engineering and Locomotive Company Electronics Division, Pune, India
Integrated Circuit (IC) Design Engineer 1 07/97-07/99
Working as Engineer in 40 years old and one of the leading Automotive Manufacturing Companies that export cars, trucks and trailers to Africa, Asia and Europe
ASIC/VLSI circuit design and Verilog RTL logic Design in one of the leading Automobile Manufacturing companies in India
Accomplishment:
Writing RTL, Synthesis and Designing and oscilloscope signal testing in Digital clock with LCD display and SGS-Thompson Micro-controller, Intel 8051; designing SGS-Thompson Micro-controller based Glow-Plug Timer for improving the fuel efficiency of Diesel Engine based SUV; Designing the PCB layout in PCAD for Light Delay Unit used for internal Lighting in cars
Developing a Rockwell Software user interface design (GUI), with control, in RS-View32, for the Crash-Test facility for safety analysis of passenger cars
Accomplishment:
RTL Synthesis, design and simulation of digital data acquisition interface in the crash test facility in an Automotive Manufacturing Company
Gas-heated Chambers
Nature of Work:
Diagnostics and Programming Allen Bradley PLC and Control Systems, studying the Graphs and profiles of temperatures on the Auto body and suggesting improvements in the heating chambers for 'baking' the automotive outer body after it gets painted
Accomplishment:
Successfully monitored and maintained the heating chambers, studied the profiles and air units and exhausts and improved the efficiency of the heating chamber.
ABB Paint Booth control system and Engineering process Design
Nature of Work:
Commissioning and Programming Allen Bradley PLCs and SLCs for controlling the 6-point highly automated paint booth
Accomplishment:
Successful completion of the project in less than 6 months while handling maintenance activities in parallel.
Conveyers
Nature of Work:
Maintenance of Conveyers for transferring the cars within the Manufacturing pipelines, and its associated Allen Bradley PLC based control systems and monitoring, studying load patterns and prevention of over-loading and conveyer stoppages
Accomplishment:
Successful maintenance of the Conveyer system leading to promotion to Electrical Engineer/Supervisor leading 5-6 operators in commissioning new car project
Control panels and Engineering Systems Architecture
Nature of work:
Designing power FETS and BiCMOS, and Analog circuits and mixed-signal integrated circuits in Automotive applications and analog amplifiers, regulators and filters used in control panels and writing Diagnostic messages in Allen Bradley Panel view for monitoring and displaying error and warning messages in conveyers, sequencing of clamps, signals from sensors, relays and actuators, robotic control signals, power information, air/water flow information, etc.
Nachi and Ogata Robots and Engineering Programmable Logic Device Design
Nature of work:
Factory Automation, Cabling of signals, RS-232 and RS-484 interface, power cables and control signals wiring, air-water supply, weld-control, commissioning and Allen Bradley PLC Programming/ladder logic, Allen Bradley Panel View and Human-Machine Interface Diagnostic messages and control, in Automobile manufacturing division making 120 cars in 1 day, and having 75 robots from Nachi and Ogata in Japan.
Accomplishments:
Successful Commissioning and selecting the digital circuits for control circuitry and leading a team of 5-6 operators in commissioning Nachi and Ogata Robots used in assembly of Tata Indica passenger cars; Developing the Diagnostic messages in Allen Bradley Panels for display in Under-body front area of the Automobile Assembly shop
Crash test facility Design Specification
Nature of work:
Commissioning and wiring of Allen Bradley PLC Panels, PLC programming/ladder logic, RS-View 32 programming to add control features for automating the crash test at 60 kmph, motor control, lighting, camera control and monitoring
Accomplishment:
Successfully conducted, monitored 1 crash test of SUV, and Commissioned the crash test facility to conduct 1 crash test every month to give feedback to the Manufacturing Division for safety norms. Meets the latest crash test standards.
Skills used/developed at Telco:
PCAD, RS-Logic, Factory Automation, Commissioning, RS-View32, Cadence, Synopsys, VHDL, VERILOG, Allen Bradley Rockwell Automation PLC and SLC Programming, ladder logic
CMOS VLSI Research Assistant, Microprocessor Research Laboratory,
Indian Institute of Technology, Madras 07/94-7/97
8051 Microcontroller:
Design and development of digital circuits using 8051 Microcontroller for digital control systems applications
Designing and simulating a 4-CLB FPGA in transistor level using Micro Magic, IRSIM, and HSPICE
Layout design at polygon level of FPGA and its Combinational Logic Blocks (CLB), with the connection matrix and switch matrix
VHDL Description of Single Cycle Data path of MIPS architecture
Accomplishment: Implemented the RISC Instruction set Architecture of MIPS Microprocessor
C programming
Writing Games software for industries; wrote 4 different games.
EDUCATION DETAILS:
MSEE from PSU, USA
Major Courses taken: Engineering Electromagnetics, Fundamentals of Digital Signal , Introduction to Neural Networks, Rapid Systems Prototyping, VLSI Digital Design, Microprocessor Architecture and Organization
BSEE from IIT, India
Major Courses taken: Device Modeling, Electric and Magnetic circuits, Introduction to Computing, Introduction to digital systems, Networks and Systems, EM Energy Conversion, Computer Organization, Microprocessors, Analog Circuits, Principles Of Communication, Solid State Devices, Control Engineering, Communications Systems, Measurements and Instrumentation, Digital Signal Processing, Power Electronics, Transmission Lines, Power Systems Analysis, Power Systems Distribution, Electromagnetics
Personal Information
Name Gourishankar Krishnamurthy
Willing to Relocate Yes
Languages Known English, Hindi, and Tamil
Residential Address 120 Cornell dr SE, #307,
Albuquerque, NM-87106
Email gourishpk@yahoo.com
gourishpk@rediffmail.com
Phone: Cell 1-408-319-0261
1-510-299-6184