Posted by on June 09, 19103 at 02:56:34:
Hello,
My name is Prakash Patil and I am seeking a VLSI design engineering position and am enclosing my resume for your consideration. I holds M.Tech. (Microelectronic) from IIT Bombay. My most recent experience is with VLSI working on back-end physical design and prior to that, I have worked more than eleven years in the electronic/computer industry.
Kind Regards,
Prakash Patil
RESUME
Full Name Prakash Hindurao Patil
Address PL5B - 1/15, Sector 10,
Khanda Colony, New Panvel (W),
Navi Mumbai. Pin Code 410 206.
State: Maharashtra,INDIA.
Phone 0091-22-745 7267. (Fixed Line)
0091-22-32754844. (Cell phone)
E-mail patilph@yahoo.com
patilph@hotmail.com
patil_prakash@vsnl.net
Web Site http://hightech.4jobs.com/PRAKASHPATIL-LNK
EXPERIENCE SUMMARY
Over one & half years of experience in physical design of Integrated Circuit (IC).
Good skills and experience of deep submicron IO pad library design, verification, using SKILL scripts. Good communication skills. Over all eleven years of experience in electronic / computer industery.
Educational Qualification:
|------------------------------------------------------------------|
| Examination |Institute |Board/University|Year |%-age/| Remarks |
| | | | | Grade| |
--------------------------------------------------------------------
|M. Tech. |I. I. T. |Indian Institute|1998- | | |
|(MICROELEC |BOMBAY |of technology | 2000 | 6.82 | I |
|-TRONICS) | |Bombay | | | |
|------------------------------------------------------------------|
|A.D.C.S.S. |Cusrow Wadia|M.S.Board |1989- | | |
|A.A. |I.O.T. Pune | |1990 | | I |
|------------------------------------------------------------------|
|B.E. |T.K.I.E.T. |Shivaji | | | |
|(Electronics)|Warana |University |1988 |56.65 |Hi-Sec. |
| |kolhapur |Kolhapur | | | |
|------------------------------------------------------------------|
AREAS OF INTEREST:
ASIC Design.
VLSI Fabrication.
ASIC Verification & Testing.
COURSES AT M.Tech.:
VLSI Design.
VLSI Technology
Computer Aided Analysis and Design
System Hardware Design
Physical Electronics
Modern Electronic Design Techniques
MOS Devices
Special Semiconductor Devices
Microelectronic Lab.
SOFTWARE PROFICIENCY:
Platforms :HP-Unix, Linux, Windows-NT (ver 4.0)
Programming Languages. : C.
Projects
1) Study of Multi-layer Multi-chip Architecture.
(Carried out at I. I. T. Bombay during year 1998-2000)
Project consists of Design & development of IC interconnects of multi-layer multi-chip architectures. The Elmore delay model is widely used in optimizing the wire sizing area of an interconnect. The wire sizing algorithms such as Optimal Wire Sizing under Elmore Delay, Greedy Wire Sizing Algorithm under the Elmore Delay and Extended Wire Sizing Algorithm under the Elmore Delay considered for the design of an interconnects in the circuit of multi-layer multi-chip architectures. The optimal wire sizing solution satisfies a number of interesting properties such as seperability, monotone and dominance properties. These properties considered at time of design of an interconnects. These algorithms are implemented to get the fruitful results. The code is written in `C' language. The results received are the delay required for the signal from source node to the destination node (e.g. driver node to the sink node in the circuit). The time complexity is calculated. User-friendly software developed for complete analysis and design of the interconnects in the circuit.
FUNCTIONAL EXPERIENCE:
* Company Name:. Philips Semiconductors, The Netherlands.
* Designation: Standard Cell Design Engineeer.
* Period of service: March 2001 to Augest 2002.
* Area of experience:
Shrink CMOS18 IO pad library Design.
CAD Library Verification. CMOS12 Library verification. Verification of new cells,
merging of new cells to Standard cell library, clean up of library cells.
CMOS18 Shrink Library verification. Verification of new cells, merging of new cells to
Standard cell library, clean up of library cells etc.
Layout developments like level shifter etc.
* Software used: Cadence Backend Qualified Design flow for Philips.( QDF 3.1)
Skill scripts, Calibre Mentor Graphics tool.
* O.S. platform used: WinNT, HP-Unix.
* Team Size:4.
* Training Undergone:
Cadence Qualified Design flow for Philips.( QDF 3.1): Three & half day of
extensive training on complete front end & backend design flow.
SKILL language : SKILL language for Cadence design tool. Extensive five days of training.
Personal Information.
Marital Status Married
Nationality Indian
Passport Id L-996080
Children One