Posted by on May 18, 19103 at 22:19:08:
Najam Zaman
404-2881 Richmond Road, Ottawa, Ontario, K2B8J5
Tel: (613) 791-6530 Email: najamzaman@hotmail.com
OBJECTIVE
In pursuit of a technical position that will utilize my skills as a physical design engineer in Digital or Analog design.
Nationality: Canadian.
TECHNICAL SKILLS
CAD/EDA TOOLS: Synopsys/Avanti (Astro, Formality, PrimeTime, Apollo, STARXT, Mars-Rail), Cadence (Simplex SOC, Virtuoso, Formal Check), Magma/Moscape (Gatescope), Mentor graphics (DesignRev, Calibre DRC/LVS), Verplex (lec), Hspice, Xilinx, Matlab, LSI Logic Flexstream tool suite.
HDL: VHDL, Verilog.
Programming Languages: Perl, Python, C/C++, AWK, TCL, HTML.
Operating System: Unix, Windows.
PROFESSIONAL EXPERIENCE
Physical Design Engineer.
LSI Logic Corporation, Kanata, Ontario, Canada. (April 2001 to present)
Design Responsibility.
· Placement, Clock tree synthesis, clock skew balancing and signal routing.
· Congestion Analysis.
· VDD IR drop and VSS IR rise power analysis and Electromigration analysis.
· Cross Talk Analysis, RC extraction.
· Static timing analysis and timing closure.
· Fixing DRC and LVS issues.
· Formal verification.
· Preparing the design for EBEAM.
Projects.
· Completed a 3 million flat gate design, (0.18 um), flip chip, frequency 233 MHz, with a Die size 15.2 x 15.2 mm. The design had 90 RAMS (async and sync), 2 PLL's, PCI cores, special purpose HSTL and BDHSTL buffers. The design had multiple clock domains with phase relation in order to meet internal and IO timing. The chip was designed for ALCATEL.
· Completed a 2 million flat gate design, flip chip, (0.18 um), 133 MHz, with a die size 12.5 X 12.5 mm. The design had 85 RAMS, 2 PLLS, PCI core and special purpose Hardmacros. The design had multiple clocks domains with stringent skew requirements on the clocks. The Chip was designed for ALCATEL.
· Completed a design that comprised of a special designed hardmacro that was repeated 16 times on the die. The die size was 12.5 x 12.5 mm and the design was 0.18um wire bond. Completed the Special designed hardmacro, which comprised of 50 thousand gates and 30 RAMS. The Chip was designed for NORTEL.
· Completed a 1 million gate flat design, (0.18 um), Frequency 79 MHz, Wire bond, and die size 8.5 x 8.5 mm. The design contained 30 RAM and 1 PLL. The chip was designed for Nortel.
Automation.
· Scripting of different procedure in the design flow using Perl and Python.
· Maintained the website for the physical design team.
Master’s in Engineering.
Concordia University, Montreal, Quebec, Canada (May 1999 to April 2001)
Major Projects
· Designed a 16x16 and 32x32 bit Constant Coefficient multiplier using VHDL and Implemented in FPGA.
Designing of a constant coefficient multiplier using KCM algorithm. High speed, single data path in Wallace tree format. Model described in VHDL. Pre and Post Synthesis Simulation using Synopsys VSS Simulator. Placement and Routing on Xilinx 4052XL-1 chip.
· Comparative analysis of Power and Delay of 1-bit Full adder cells using structured approach.
Power and delay analysis of different XOR and XNOR modules in Cmosis5 tech. Then using the best Design to build a Full Adder cell. Exhaustive simulation of all possible design in Cadence, Hspice, And Awaves. Building layout (Cmosis5). Post layout simulation of the design.
· Formal Verification of Alternating Bit Protocol (ABP).
ABP Code was given in Verilog for VIS (verification interact with synthesis), Modification of the code to make it acceptable in Formal Check. Writing various properties to verify the functionality and behavior of the code.
Major Courses.
Telecommunication and Networks:
· Local Area Networks (ATM, Sonet, X.25, TCP/IP, Ethernet).
· Principles of Digital Data Transmission (FSK, PSK, ASK, Channel Equalization etc).
· Error detecting and correcting codes (Convolutional codes, BCH, Reed-Solomon, TCM).
· Error Detection & Estimation theory.
Digital System Design & VLSI:
· Design of Digital Systems (ASIC & FPGA Design techniques using Synopsys, Xilinx & Cadence).
· Introduction to VLSI systems (CMOS circuits and logic design, CMOS process technology BICMOS, SRAM & DRAM cells).
· VLSI process technology.
· VLSI material technology.
· Microprocessors and their applications (Motorola 68000 CPU architecture and instruction set).
Verification:
· Hardware Formal Verification (ROBDD, Model checking & Theorem proving techniques).
Digital Signal Processing
· Digital Signal Processing (Design of digital filters, Discrete Fourier transform, Fast Fourier transform, Time, Z transform and Laplace Domain analysis of signals).
Hardware Engineer
United Technova Pvt. Ltd, Karachi, Pakistan. (March 1997 to April 1999)
· Designing of PC interface & Microcontroler boards and program them on the customer requirement. Hardware & Software installation for Local Area Networks (Terminals, Hubs, Switches, and Cables), Customer Support
EDUCATION
M.Eng. Electrical Engineering. (May 1999 to April 2001)
Majors in Digital Design and Telecommunication.
Concordia University, Montreal. Quebec, Canada.
GPA: 3.5
B.Eng. Electrical Engineering (Aug1993 to Aug 1998)
NED University of Engineering and Technology, Karachi, Pakistan.
PUBLICATION
Najam-uz Zaman, Dr. A.J Al-Khalili, "32-bit Constant Coefficient Multipliers", IEEE Region 10th International Conference on Electrical and Electronic Technology, TENON 2001, (Signal, Image and Speech processing) Singapore Aug. 2001.
REFERENCES
Available on Request.