Posted by on April 18, 19103 at 18:15:18:
CURRICULUM VITAE
Gourishankar Krishnamurthy Home: (510)4906630
Email: gourishpk@yahoo.com Cell : (408)3190261
OBJECTIVE:
To apply my Electrical Engineering skills as a full-time/Contract Engineer in the areas of ASIC logic Design, CMOS VLSI Design
SKILLS SUMMARY:
CMOS VLSI circuit design:
Cadence Virtuoso for Schematic Editor (opus schematic editor), Hspice for functional and timing simulation, Powermill for Power measurements and estimation, PathMill for timing analysis, EM-tool for checking Electro-migration limits, Simplex for Static EM, IR and Signal EM, Chrysalis for formal verification, Calibre for Physical Design Verification (PDV) flow for drc, lvs, schematic and layout erc, noise-tool for noise analysis
ASIC/ Logic design:
Xilinx top-down design tools for FPGA design, Altera Max-Plus-II for CPLD design, Verilog-XL for functional simulation and test-benches, Cadence Design Analyzer, and Modelsim
Board design:
Cadence Allegro PCB Layout, PCAD for PCB design
Programming:
VERILOG, VHDL, Perl
EXPERIENCE:
Sun Microsystems, Sunnyvale, CA
Member of Technical Staff, Hardware 01/01 – 12/02
Working on logic design in the multiple full custom, low power very high-speed digital blocks in the next generation UltraSPARC microprocessor family with 8 Metal Layers at the Sun Microelectronics Division
Design of Integer execution unit (IEU) and Arithmetic and logic unit(ALU) datapath and evaluation of power, area and delay of two different adders and design, simulation, functionality, critical path analysis in Integer Execution Unit
Accomplishments: Completed RTL design, synthesis and simulation and CMOS design of static adder with low threshold voltage evaluation and also using dynamic adder and comparing the results and presentation of IEU datapath comparison of the two different style of implementation
Design and characterization of mega-cells;
Accomplishments: Completed characterizing a mega cell ‘pipctl’, which is the valid and dispatch block. This involved working in the mega-cell team and RTL and circuit specification, schematic capture, transistor-level and static gate-level timing analysis, EM/IR flow using Simplex, noise analysis using noise-tool, checking rtl vs. schematics for equivalence using Chrysalis, working with mask designers, block place and route, physical verification (lvs, drc, erc) using Calibre, holding reviews and documenting work, and final delivery of the mega-cell.
Design and development of Perl-based script for verifying Electro-migration limits
Accomplishments: Designed a running script for checking EM limits for metal layers, vias and contacts.
Design of different types of flops and design of pulsed-flops for next generation low-power UltraSPARC Microprocessor
Accomplishments: Designed and modified the critical path involved in the integer execution unit. This involved studying legacy flop designs at Sun, modifying RTL and designing pulse flops for use in critical paths.
Interacting with the Global SRAM team in getting the specifications for the cache designs and register files and studying and discussing the circuit implementations with the designers.
Ran the clock-flow in mega cells, clusters, and blocks in the Microprocessor. Running at transistor level, this tool was used to test the different hierarchies in the Microprocessor for clock skew for different levels of clock routing.
Accomplishments: Helped the clock team in running valuable test routines to check at the clock skew numbers and was critical to the tape-out of the Microprocessor
Tools used At Sun Microsystems: Calibre for Physical Design Verification(PDV) flow, Hspice, Powermill, PathMill, EMtool, Simplex for Static EM, IR and Signal EM, PERL for scripting, Verilog-XL, Cadence Design Analyzer, Chrysalis, mkgmv
Center for Electronic Design, Communication and Computing (CEDCC)
University Park, PA 07/99 – 04/00 and 09/00-12/00
Part-time Research and Development Engineer
Working on logic design in the multiple full custom, high speed digital blocks:
Working in Smart memory architecture (processor with embedded memory design), selecting dual ported SRAMs and regular SRAMs for image processing applications
Accomplishment: programming on-board Xilinx FPGA & RISC Processor, selection of on-board memory, coding RTL, synthesis using Synplify, Place and Route using Programmable IC (PIC) flow, design, verification, and back-annotation of design. (WEB SITE: http://www.cedcc.psu.edu/smartdimm); this involved improving the processor memory speed from a standard PCI interface bandwidth to PC100 access
Working in Researching I/O and peripheral buses IEEE1394, USB, Firewire,IDE, PCI, bus and AGP and memory buses PC100
Accomplishment: Presentation of the bus study and recommendations of the appropriate bus architectre for smart-memory applications in Image processing of MPEG/JPEG, FPGA accelerators, and Network Interface Applications.
Tools used at CEDCC: Synopsys/Synplify, Cadence, Altera CPLD and Xilinx Programmable IC (PIC) flow for top-down design, Modelsim, VHDL, Allegro, and HP Oscilloscope
Marconi Communications, Warrendale, PA
Summer intern 05/00-08/00
Powering up an OC-48 Network Module and testing the board for clock skews, signal integrity, slew rates, etc
Accomplishment: Successfully powered up 5 network modules, and programmed the boot-code in the Xilinx virtex FPGA
Modifying the VHDL test bench of a loop-back mechanism used in OC-48 rate Network Module
Accomplishment: Running simulation tests, and conclusion resulting in the modification and demonstrating loop-back feature
Designing Xilinx Virtex FPGA based Network Modules and writing pragmas for diagnostic scripts for programs running in Xilinx Virtex based FPGA to be used in OC-48 rate Network Modules
Accomplishment: RTL design of the core, synthesis, timing verification, Place and Route, Back-Annotation and verification of the design.
Tools used at Marconi Communications: Modelsim, VHDL, Allegro, and HP Oscilloscope
Tata Engineering and Locomotive Company
Electronics Division, Pune, India
Integrated Circuit (IC) Design Engineer 1 07/97-07/99
Working as Engineer in 40 years old and one of the leading Automotive Manufacturing Companies that export cars, trucks and trailers to Africa, Asia and Europe
Verilog RTL logic Design in one of the leading Automobile Manufacturing companies in India
Accomplishment: Writing RTL, Synthesis and Designing Digital clock with LCD display and SGS-Thompson based Micro-controller; designing SGS-Thompson Micro-controller based Glow-Plug Timer for improving the fuel efficiency of Diesel Engine based SUV; Designing the layout in PCAD for Light Delay Unit used for internal Lighting in cars
Electronic circuits Commissioning in Automobile manufacturing division making 120 cars in 1 day, and having 75 robots from Nachi and Ogata in Japan.
Accomplishments: RTL Synthesis and selecting the digital circuits for control circuitry and Leading a team of 5-6 operators in commissioning Nachi and Ogata Robots used in assembly of Tata Indica passenger cars;
Developing a Rockwell Software GUI, with control, in RS-View32, for the Crash-Test facility for safety analysis of passenger cars
Accomplishment: RTL Synthesis, design and simulation of digital data acquisition interface in the crash test facility in an Automotive Manufacturing Company
Gas-heated Chambers
Nature of Work: Diagnostics and Programming Allen Bradley PLC and Control Systems, studying the Graphs and profiles of temperatures on the Auto body and suggesting improvements in the heating chambers for 'baking' the automotive outer body after it gets painted
Accomplishment: Successfully monitored and maintained the heating chambers, studied the profiles and air units and exhausts and improved the efficiency of the heating chamber.
ABB Paint Booth control system
Nature of Work: Commissioning and Programming Allen Bradley PLCs and SLCs for controlling the 6-point highly automated paint booth
Accomplishment: Successful completion of the project in less than 6 months while handling maintenance activities in parallel.
Conveyers
Nature of Work: Maintenance of Conveyers for transferring the cars within the Manufacturing pipelines, and its associated Allen Bradley PLC based control systems and monitoring, studying load patterns and prevention of over-loading and conveyer stoppages
Accomplishment: Successful maintenance of the Conveyer system leading to promotion to Electrical Engineer/Supervisor leading 5-6 operators in commissioning new car project
Automotive products design
Nature of Work: Designing automotive digital circuits in the Electronics Division of Telco.
Accomplishments: Designing Digital clock with LCD display. Designing SGS-Thompson Micro-controller based Glow-Plug Timer for improving the fuel efficiency of Diesel Engine based Sports Utility Vehicle. Designing the layout in PCAD for Light Delay Unit used for internal Lighting in cars
Panel view
Nature of work: Writing Diagnostic messages in Allen Bradley Panel view for monitoring and displaying error and warning messages in conveyers, sequencing of clamps, signals from sensors, relays and actuators, robotic control signals, power information, air/water flow information, etc.
Nachi and Ogata Robots
Nature of work: Factory Automation, Cabling of signals, power cables and control signals wiring, air-water supply, weld-control, commissioning and Allen Bradley PLC Programming, Allen Bradley Panel View and Human-Machine Interface Diagnostic messages and control, in Automobile manufacturing division making 120 cars in 1 day, and having 75 robots from Nachi and Ogata in Japan.
Accomplishments: Successful Commissioning and selecting the digital circuits for control circuitry and Leading a team of 5-6 operators in commissioning Nachi and Ogata Robots used in assembly of Tata Indica passenger cars; Developing the Diagnostic messages in Allen Bradley Panels for display in Under-body front area of the Automobile Assembly shop
Crash test facility
Nature of work: Commissioning and wiring of Allen Bradley PLC Panels, PLC programming, RS-View 32 programming to add control features for automating the crash test at 60 kmph, motor control, lighting, camera control and monitoring
Accomplishment: Successfully conducted, monitored 1 crash test of SUV, and Commissioned the crash test facility to conduct 1 crash test every month to give feedback to the Manufacturing Division for safety norms. Meets the latest crash test standards.
Skills used/developed at Telco: PCAD, RS-Logic, Factory Automation, Commissioning, RS-View32, Cadence, Synopsys, VHDL, Verilog, Allen Bradley Rockwell Automation PLC and SLC Programming
CMOS VLSI Research Assistant, Microprocessor Research Laboratory,
Indian Institute of Technology, Madras 07/94-7/97
Designing and simulating a 4-CLB FPGA in transistor level using Micro Magic, IRSIM, and HSPICE
Accomplishment: Designed an FPGA and its Combinational Logic Blocks (CLB), with the connection matrix and switch matrix
VHDL Description of Single Cycle Data path of MIPS architecture
Accomplishment: Implemented the RISC Instruction set Architecture of MIPS Microprocessor
EDUCATION
B.S in Electrical Engineering
Indian Institute of Technology, Chennai (IIT Madras) India 07/93- 07/97
M.S in Electrical Engineering
Penn State University, University Park, PA 07/99-12/00
PERSONAL SKILLS
Good at Analytical and Logical Thinking
Possess good Listening and understanding skills
A Good Team builder and has nice leading capacity
Management and leadership skills
Effective written and verbal abilities
Strong organizational and interpersonal skills.
HONORS
National Social Service (NSS) member as an Undergraduate student
Blood Donation Coordinator as an Undergraduate student
PERSONAL INFORMATION
Name : Gourishankar Krishnamurthy
Sex : Male
Age and DOB : 27, 04 July 1975
Languages Known : English, Hindi, and Tamil
Marital Status : Married
Father’s Name : Krishnamurthy Padmanabhan
Father’s Occupation : Regional Director, AMD, India
Residential Address : 39600 Fremont Blvd, #101,
Fremont, California – 94538
USA
Immigration Status : H1-B Visa
Email : gourishpk@yahoo.com
Phone: Home : 510.490.6630
Cell : 490.319.0261
Date: 18th April 2003
Place: Fremont, CA Gourishankar Krishnamurthy