Posted by on March 16, 19103 at 05:57:26:
CURRICULAM VITAE
1. Name : MUDIT SAKSENA
2. Father’s Name : Dr. K.K.Saksena
3. Date of Birth : 12 February 1974
4. Nationality : Indian
5. Marital Status : Unmarried
6. Mailing Address : 66-B, Gyan Khand- IV
Indirapuram
Distt. Ghaziabad - 201010, India
Telephone: +91-120-2605011
Mobile Phone:+91-9811839026.
E-mail:muditsaksena1@rocketmail.com
muditsaksena1@rediffmail.com
7. Education :1. Bachelor of Engineering (Electronics and Communication); Course completion in 1999; from Bangalore University, India
2.Diploma in Systems Programming and VLSI Design -from Electronics Research and Development Center of India (ER&DCI), NOIDA (India), of Department of Information Technology, Ministry of Communications and Information Technology, Government of India - completed January 2003. (VLSI Grade A+)
Specific Courses studied: (i) VLSI Design: (a) Digital System Design, (b) Verilog, (c) VHDL, (d) Logic Synthesis, (e) FPGA Based Design, (f) CMOS VLSI Design (g) SPICE (h) Analog IC and (i) Full Custom IC Design
3 Training Courses: C++, Java & Web Application Development (2000-2001) from NIIT, at Ghaziabad.
8. VLSI Work/Experience: 1. EDA Tools:
Semi Custom IC Design - 1. LDV 3.2(for NC verilog, NC VHDL and simulator (NC SIM)) and Ambit Build Gates (for logic synthesis).
Full Custom IC Design – Affirma (Analog Circuit Simulator), Composer schematic and composer symbol (for Schematic design), Hspice (for simulation of analog schematic design), Diva/Dracula (Design rule check for layout design), Virtuoso (Layout Design), Diva (Layout vs. schematic), and Silicon Ensamble (Floor – planning, Placement & Routing).
FPGA - Xilinix = FPGA (Spartan - II) (from XILIX corp.)
Exposure to Sun Solaris platform
2. Skills :
Digital Design, verilog HDL Simulation and Synthesis, ASIC Design Methodology, verifying, and documenting FPGA/CPLD, CMOS, Design issues (Latch up, ESD, Anteena, Electromigration, Crosstalk etc.) and Active Elements Modeling using HSPICE/PSPICE.
3. Projects:
(A). Design of CODEC for Transmission codes - Design of codec can be said to follow top-down approach, where it’s functioning is divided into subsections, which are all connected to produce the required functionality. It should have the property of encoding the input data stream at the transmission end into RZ or Manchester format as per choice and decode it suitably at the receiving end. This chip will replace the traditional interface hardware design with digital IC’s. The code is written in VHDL and simulated on XILINX (Foundation series F3.1i) and CADENCE (LDV 3.2) tools, successful results were obtained on simulation with accurate waveforms - Two team members - Duration 25 days at ER&DCI
(B). Digital Alarm Clock – A total of 29 flip-flops (18 for clock time and 11 for alarm time) are needed. The alarm output goes high when the current value of time is equal to the alarm time the alarm should stay on until either the alarm enable signal goes low (turning off) or after period of one minute has elapsed when left on. If power is lost, and then powered up again, it should display the time 00:00:00 and the flashing signal should be activated high This causes the display to flash and so indicate that the alarm clock’s time needs to be set. Coded and tested using both Verilog and VHDL and CADENCE (LDV 3.2) tool. - Two-team members- duration 7 days at ER&DCI
(C). Implementation of different Multipliers and Divider algorithm (8 x 8) – The following algorithms were coded and tested using both Verilog and VHDL and CADENCE (LDV 3.2) tool. (1) Shift and add multiplication algorithm for combination or sequential circuits. (2) Booth’s multiplication algorithm for sequential circuits. (3) Shift and Subtract division algorithm for combination and sequential circuits. Successful results were obtained –Two-team members- duration 14 days at ER&DCI.
(D). CMOS SRAM DESIGN- The number of cells arranged in rows & columns constitute the memory .The basic cell is typically a transistor flip-flop or a circuit capable of storing one bit of information The cell used in CMOS static RAM is associated with a sense amplifier & pre-charged circuitry. Eight bit CMOS level SRAM was designed using CADENCE Composer Schematic and Affirma.The circuit performed according to the given specifications & operated successfully - Three-team members- duration 30 days at ER&DCI
(E). Implementation of different decoders and counters using XILINX wedpack and XILINX FPGA analyzer.
9. Previous Employment : Position:
1. Manager (01 July 01 - 31 July 02)
2. Deputy Manager (01 July 00 - 30 June 01)
3. Executive (01 Nov 99 - 30 June 00)
Company: AMBIENCE AGENCIES (P) LTD, NOIDA - a Hindustan Computers Limited (HCL) channel partner.
Job:
The job requirement consisted of (i) procurement, assembly, installation, maintenance and upkeep of computers and electronic equipment; (ii) networking solutions, management and optimization service covering intranet, internet and hardware solutions, specialized off-the-shelf packages and customized software solutions; (iii) sales, marketing and customer service covering income generation planning, devising sales targets, developing marketing effort through personal contracts, including advertising, organizing sales carnivals, arranging deliveries to the customers and post-sale effort; and (iv) administration and personnel management. In Sales and Marketing my primary duty was to concentrate on 4 Ps of marketing - product, price, promotion and physical distribution with particular emphasis on the last two. The product component basically aimed at providing an appropriate product mix to the consumers. The pricing was handled only as a part of promotional mix with product prices already decided by manufacturers in consideration of cost, competition and demand. Promotional mix handled included personal selling, sales promotion, publicity and public relations. Physical distribution involved management of marketing channels, inventory control and translocation of physical supplies.
10. Research Interests : Analog & digital VLSI circuits, advanced electronics & semiconductor devices.
(Mudit saksena)