Posted by on March 16, 19103 at 04:40:51:
Prakash Chand Kuve
Objective : Position as an Analog/Mixed signal Design engineer in a
professionally managed organization. I am looking forward to an opportunity
where I can utilize my skills in the areas of clock generation and distribution
circuits/Synchronization circuits and contribute effectively to the success of
the organization.
3+ years of total experience in IC design Industry.
Analog/Mixed-signal design Engineer.
Specializing in Clock Generation and distribution circuits.
Synchronization circuits (PLLs, DLLs, FLLs).
SRAM design experience.
Technology characterization circuits.
High-Performance digital design.
Design Verification Expertise (Calibre LVS, DRC verification decks, Magic
technology files).
Indepth CMOS Process Knowledge (Field of expertise being silicides and buried
contacts).
Linux/Unix system knowledge, OpenSource EDA tools.
Perl, Perl/Tk, Tcl/Tk scripting experience.
SPICE/TSPICE simulations, Analog circuit layouts, Schematic capture, Plotting
tools.
Test and data Analysis, Wafer probing with HP4156 Tester.
Independent Design Consultant May 2002 - Current date
Working as an Independent Circuit Design consultant, assisting MultiGiG LTD
(www.multigig.com) in developing their clock-generation and distribution
architecture called the Rotary Travelling Wave Oscillator Technology (RTWO). The
task of a clock distribution system s to deliver the critical clock edge to all
places on the chip at the same time, while also keeping he clock signals sharp
and free of distortion. Rotary Traveling Wave Oscillators (RTWOs) represent a
new transmissionline approach to gigahertz-rate clock generation and
distribution [1]. Multigig LTD is a Technology startup based in U.K.,
specializing in multigigahertz rate circuit design I.P. Worked on the design and
simulations of a Frequency Locked Loop (FLL) circuit module which would get get
the RTW oscillator locked onto an external reference-frequency. Coarse
frequency-tuning was done through switched capacitors and fine tuning via
varactor control.
Design Engineer at KarMic Design Centre (KDC) September 2000- May 2002.
Worked at KarMic Design Centre (KDC), a company focused on analog,
mixed-signal, high-performance digital and RF circuit designs. Was part of a
team of seven people who were the very first employees at the company.
Projects done at KDC:-
TDSRAM design Project:
Was part of a design team that worked on design, simulation and layout of
Technology Development SRAM (TDSRAM) circuit module. TDSRAM was a technology
characterization test vehicle meant for evolving technologies. The Bitcell
Failure Patterns in the SRAM automatically provided information to a Process
Integration Expert regarding fine-tuning required in the process recipe.
Also worked at Testchip Technologies Inc, Dallas, USA, from January 2000 to June
2000 as a part of the KDC team to coordinate the efforts of the design teams
located at India and the US. Testchip Technologies Inc is a company focused on
developing innovative circuit designs which assist the Chip fabrication units in
accelerating their Technology development efforts.
Analog Circuit-suite project:
Was part of a design team that worked on a full Analog circuit-suite meant
for Analog characterization of an evolving Process technology. This suite of
circuits was one of the very first to be fabricated on that Technology and was
used to validate the models as well as the Design rules of the process. Worked
on design, simulation and layout of a fully-digital Delay Locked Loop (DLL)
circuit module which was meant as a bench-mark circuit for the process.
Fuse-SRAM design project:
Was part of a design team that worked on a Fuse-SRAM project. This was a
design where the agglomeration property of Titanium-silicide poly was used to
program a bitcell in an SRAM. This gave the SRAM a ROM-like property with the
speed advantage of an SRAM.
Design Verification Efforts:
Worked part-time on Calibre LVS, DRC verification decks and Magic Technology
files so that the designs and layouts complied with the foundry-specific rules.
Handled the complete verification and final tapeout of the designs. Also was
instrumental in customising an Open-Source Layout Editor(Magic) to do layouts
for cutting-edge technologies like the 0.15um and 0.13um technologies which
inherently have very special design rules. This effort resulted in
substantial cost savings for the company.
Trainee Engineer at KarMic Training Centre August 1999-august 2000
KarMic Training Centre(KTC) is the Training Wing of KarMic Design Centre, set
up to provide indepth training in IC design to EE graduates. The training period
was of 1 year and the trainees were taught all aspects of IC design with an
emphasis laid on Transistor-level design.
Themes covered during training:
Analog circuit Design.
Memory Design.
High-performance digital design.
RF design.
Was part of a team of 3 people that designed a Mixed-signal chip meant for
low cost Internet access and telecom applications. My contribution included
design, simulation and layout of the Analog Signal driver into a flat cable.
This design was accorded the Best Design award at VLSI Design Contest, 2000,
held at Bangalore, India. The training was equivalent to a Master's course in
Chip Design.
Education:
Bachelor's degree in Electronics and Communications Engineering from M I T,
Manipal,Mangalore University, INDIA.
References:
Name: Dr. S S Mahant Shetti
Company:KarMic Design Centre
Position:Managing Director
email:mahant_shetti@vsnl.com
Name: Mr. John Wood.
Company: MultiGiG Ltd.
Position: Managing Director
email: john.wood@multigig.com
Name: Mr. Muthukrishnan C
Company: Sage Design Systems
Position: Managing Director
email: samy@genesis-microchip.com
[1] John Wood, Terry C Edwards, Steve Lipa. "Rotary Travelling Wave Oscillator
Arrays: - A New Clock Technology" IEEE JSSCC, Nov, 2001.