Posted by on December 18, 19102 at 07:09:47:
Experience Summary:
· 3+ years of experience in VLSI design, having worked extensively on Development of IP cores , FPGA implementation,Verification and ASIC Physical design.
· 6 months experience in library development, model development, Geometry development and PCB CAD.
· 3 years experience in designing and servicing of UPS, Inverter.
· 3 years experience in servicing of Bio-Chemical Instruments like Dissolved Oxygen, pH meter, and Flame Photometer.
Technical Skills:
· HDL language Verilog HDL
· Good Knowledge of Digital Design
· Specification to RTL
· Gate level simulation & Verification
· Worked on Simulation tools like VCS from Synopsys
· Knowledge of formal verification tool Verplex
· Worked on Chipscope Analyzer, Logic Analyzer
· Knowledge of XILINX FPGA design
· Knowledge of Physical Design
· Worked on Physical Design tool MAGMA Blast Fusion
· Worked on Physical Design tool Cadence Virtuoso – cell creation
· PERL, M-Tcl scripting
· Library development –Symols & Geometries
· Architectural design and Geometry creation for Printed Wire Board
· Experienced in using Mentor Graphics Design Manager, Design Architect, and Librarian
Work Experience:
D’gipro Systems Pvt. Ltd, [August 1999 to present]
Physical Design Project:
Usb Interface:
Input : Verilog Netlist
Output :GDSII
Title : USB Interface
Tool : Magma – Blast Fusion,Blast RTL, Blast Noise
Client : Dgipro Systems Pvt Ltd
Location : Bangalore.
Design size : 40k std cells, 4 macros
Process : 0.18um,6 layers
Clock : 48 MHz.
Target slack : 170 ps
Target skew : 200 ps
Sub-targets : To fix all the timing violations and DRC,LVS
Bluetooth:(Baseband Controller)
Input : Verilog Netlist
Output :GDSII
Title : Baseband Controller
Tool : Magma – Blast Fusion, Blast RTL, Blast Noise
Client : Dgipro Systems Pvt Ltd
Location : Bangalore.
Design size : 200k std cells, 3 macros
Process : 0.18um,6 layers
Clock : 30 MHz.
Target slack : 420 ps
Target skew : 450 ps
Sub-targets : To fix all the timing violations and DRC,LVS
Euro2000(Aircraft control):
Input : Verilog Netlist
Output :GDSII
Title : Euro2000(Aircraft control)
Tool : Magma – Blast Fusion, Blast RTL, Blast Noise
Client : Dgipro Systems Pvt Ltd
Location : Bangalore.
Design size : 800k std cells, 9 macros
Process : 0.18um,6 layers
Clock : 250MHz.
Target slack : 50 ps
Sub-targets : To fix all the timing violations and DRC,LVS
Task performed for all Projects:
1.Quality Analysis on Provided Library
2. Setting up design rules from Technology documents.
3. Floorplanning
4. Power planning
5. Optimization & Timing check
6. Clock tree synthesis
7. DRC & LVS Clearance
8. Signal Integrity analysis for Cross talk & EM violations
9. Formal Verification
Library Cell Creation: at ITI fab
Basic CMOS cells were created for Tool evaluation project
Tool : Cadence – Virtuoso
Magma Training Project:
A netlist of a sample design of 250k gates was given to generate GDSII.
GDSII was generated without any violation and warning.
Logic Design Projects:
DGDSP2100 (Digital Signal Processor)
ADSP-2100 is a 16-bit, microprocessor optimized for DSP.
· Separate Program and Data Buses, extended off-chip.
· Single-cycle direct access to 16Kx16 of Data Memory.
· Internal instruction cache, of size 16x24bits.
· Multifunction Instructions.
· 125ns Cycle Time.
Job Responsibility: Desgin and verification
· Designing Instruction Decoder Block
USB INTERFACE:
Features:
· Fully Compatible with USB Specification
· Full speed (12 Mbps) and high speed (480 Mbps)
· Support for 13 endpoints including upto 12 user configurable endpoints.
· Supports Bulk, Interrupt and Isochronous transfer.
· On-chip Endpoint DPRAM
· Optimized for FPGA implementation
Job Responsibility: Verification and Physical Testing
· The Bus Function Models were developed in Verilog.
· Implemented in Xilinx FPGA
· Environment setup for Physical testing
· Board designing for Tranceiver Interface
Memory Management Unit (MMU):
The DG68851 is a high performance Paged Memory Management Unit
(PMMU) designed for demand-paged virtual memory environment The core is similar in
functionality to Motorola 68851.The cache with CAM is used for the multitasking
environment i.e the MMU can be used with the multitasking micro controller.
Features:
· Fast logical-to-physical address translation
· 32-bit logical and physical addresses with 4-bit function code
· Wide selection of page sizes from 256 bytes to 32K bytes
· Fully associative, 32 entry on-chip address translation cache
· Automatic update of the on-chip translation cache from external translation
tables.
Job Responsibility: Design and Verification
· The RTL level code was written in Verilog.
· The MMU core was tested by giving test vectors. The test
bench was written in Verilog.
· Implemented in FPGA.
Infra-Red Data Association
The IrDA Control system operates at a transmission speed of 75.0 kbps. The data to be transmitted is coded by the 16-Pulse Sequence Modulation (16PSM) scheme, multiplied by a subcarrier and then output by the infrared transmitter. A frequency of 1.5 MHz is used for the subcarrier. The 16PSM scheme is able to reduce the interference between an IrDA Control system and a Remote Control System that uses frequencies in the 33kHz - 40kHz band
Features.
· Distance and range equivalent to that of current Uni. -Directional infrared
remote control units.
· Half-duplex Transmission for free space communication between two
independent nodes.
· Bi-directional communication.
· Data transmission rate up to 4.0 Mbps.
Job Responsibility: Design and Verification
· The RTL level code was written in Verilog.
· The IrDA core was tested by giving test vectors. The test
bench was written in Verilog
· Implemented in FPGA.
Library development project (Honeywell):
The graphical symbols and models for the digital and analog electronics components varying from Simple flip-flop ICs to medium complex PLDs ,memory to complex Microprocessors and microcontroller were created using IEEE standards and Honeywell specification.
Once the functional model was developed they were simulated and tested for both functionality and for timing characteristics.
The Geometry (footprints) for Printed Wire Board were created using Librarian tool supplied by Mentor Graphics.