Posted by on November 14, 19100 at 04:38:08:
Ideally between 3 and 5 years experience of digital ASIC design using HDL/synthesis
Can clearly demonstrate experience of the whole design cycle from concept through to specification, implementation, synthesis test and manufacture.
Ideally would have good experience of designing in VHDL (not necessarily 5 years). Mixture of VHDL and Verilog HDL would be advantage.
Designing in a mixed-signal environment would be an advantage
Ideally experienced in Modelsim/ Synopsys toolset but prepared to give training in our own toolset
Experience of a UNIX environment
The Person
Leadership qualities – from a technical viewpoint
Professional approach
Good communication skills
Strong academic background – almost certainly a 2 (i) or above in a relevant subject
Self starter – able to manage their own time effectively
Interest and enthusiasm