Posted by on November 26, 1999 at 07:41:14:
Dallas, USA
Texas Instruments has always led the field in the development of the electronics that have transformed everyone's lives and are the world leader in Digital Signal Processing Solutions. DSPS, used heavily in wireless communication and hard-disk drives is a major technology fuelling growth in new applications such as internet appliances, TV set-top boxes and cameras.
To continue to innovate, Texas Instruments need engineers that are the best in their field and they offer an opportunity to play an active role in designing the future of electronics and in turn shape the way that people live in the future.
Responsibilities:
Excellence in development & productization of advanced process technologies
Lead team responsible for developing & supporting Cadence PDKs, DRC & LVS verification decks for state-of-the-art mixed signal process technologies
Establish & improve technical & business practices to improve Cadence PDK, DRC/LVS/PEX verification deck quality, & reduce development cycle time
Work with SPG & LTD program managers to support Cadence design kits for their process technologies
Cadence PDK development: Supervisor development & support of design kits (CDK) that represents physical & electrical properties of process technology's supported component list
Manage development & fanout of associated engineering standards (PDK standards) in close cooperation with EDA development & support teams
Work with program managers & development manager to develop & update on-line process technology documentation
Design Rule Development: Develop design rule (DRC/DV), & layout versus schematic (LVS/SV) descriptions (rule sets) used with verification software to check that integrated circuit (IC) physical layout meets applicable design rules & correctly represents schematic design rules & correctly represents schematic design
Develop regression tests & other QC tools for verifying deck quality
Parasitic Extraction Development: Develop rules which extract parasitic device information directly from IC layout. These parasitics are now dominant effect on analog & digital performance in state of the art ICs
Continuous Improvement: Work closely with design engineers & process development engineers to solve problems using CAD environment & process technology
Develop technical plans for making component additions & quality improvements to CAD environment
Skills required:
Prefer technical supervisor or team leadership experience
Familiar with CMOS &/or BiCMOS Process/Fabrication Technologies & typical design rules
Development & debug of DRC, LVS, & parasitic extraction decks in Dracula, Vampire, DIVA, Checkmate or similar tool
IC layout tools such as MAGIC, Cadence, Mentor, etc. Cadence transistor-level design tools
UNIX, PERL, C script development
Working knowledge of analog & mixed-signal IC design
Clear oral & written technical communications skills
Project planning skills
Empirical problem solving skills
TI specific process technologies & design rules
TI specific verification tools
TI specific Cadence-based flows & PDK Standards