Posted by on June 14, 19101 at 11:59:29:
(Mobile Telephone) (0917) 5412370 (Home Telephone) (632) 9130199
(Office Telephone) (632) 4351064
(Email) wabing@eudoramail.com
WORK EXPERIENCE:
April 2001-present SENIOR SCIENCE RESEARCH SPECIALIST II,
Advanced Science and Technology Institute (ASTI)
Department of Science and Technology (DOST)
Project leader for the ASIC implementation of 32-bit RISC Pipelined Microprocessor using VHDL design entry
Conducts trainings for the industry and the academe in the field of Microelectronics
Network administration
April 2000-March2001 SCIENCE RESEARCH SPECIALIST II,
Advanced Science and Technology Institute (ASTI)
Department of Science and Technology (DOST)
Project leader for the ASIC implementation of 32-bit RISC Pipelined Microprocessor using VHDL design entry
Conducts trainings for the industry and the academe in the field of Microelectronics
Network administration
1998 2000 RESEARCH ASSISTANT
Intel Microprocessors Laboratory
University of the Philippines, Diliman
Designed and simulated a 32-bit, 5-stage pipelined RISC microprocessor using Cadence Design Tools
Network administration
EDUCATION:
1994 - 2000 UNIVERSITY OF THE PHILIPPINES, Diliman, Quezon City
Bachelor of Science in Electronics and Communications Engineering
1993 1994 UNIVERSITY OF SANTO TOMAS, Sampaloc, Manila
1989 - 1993 XAVIER SCHOOL, Greenhills, San Juan
High School Diploma
LICENSURE EXAM TAKEN:
Nov 4-5, 2000 Electronics and Communications Board Examinations
passed
PUBLISHED PAPERS/CONFERENCE PAPERS:
32-bit, 5 stage Pipelined RISC Microprocessor", Philippine Engineering Journal
Shifting to Innovation : Putting the Philippine Microelectronics Industry at the Forefront of Development,
Philippine Engineering Journal
A VHDL Model of a 32-Bit, Five-Stage Pipelined, Reduced Instruction Set Computer (RISC),
1st ECE Conference, De La Salle University
SKILLS:
FPGA and ASIC Design using Hardware Descriptive Language
Knowledgeable in Cadence VHDL Simulation Tools, Ambit BuildGates Synthesis Tool, Galileo Synthesis Tool, Summit Visual HDL Tool, Xilinx XACT Design Editor, Cadence Leapfrog Simulator, Silicon Ensemble Place and Route Tool, CTGen, NCVHDL
Digital VLSI Design
Knowledgeable in L-edit, Cadence Virtuoso Layout Editor
Microprocessor-based Designs
Knowledgeable in Motorola 68000 assembly language, Zilog Z80 programming
Turbo C programming and Programmable Logic Control Design
Knowledgeable in using oscilloscope and signal generator
Basic Windows NT administration
Basic HTML and Visual Basic programming
SEMINARS ATTENDED AND TRAININGS CONDUCTED:
1st ECE Conference, December 2, 2000, De La Salle University
In-House Cadence Tools Training, September 2000
VLSI Design Training, June 4 July 7, 2000 , ASTI Training Room
Gender Sensitivity Seminar, May 12, 2000, ASTI Training Room
K-Economy Conference, May 8, 2000, Manila Hotel
Cadence Software Tools Training, April 4-19, U.P. Diliman
VCTI Roadshow: Digital Design Using VHDL April 29 May1,2001
ORGANIZATIONS:
Institute of Electronics and Communications Engineers of the Philippines
Member, 2000 present
UP Alumni Engineers
Lifetime Member
UP Student Catholic Action
Member, 1995-2000
Asst. Treasurer, 1996 - 1997
UP CIRCUIT
Founding Member