Posted by on February 25, 19103 at 08:07:10:

RESUME

C.GNANASEKARAN
E-mail: cgnanasekaran@yahoo.co.in
Phone: 080-5247186

Objective
Looking forward for a career change, where my RTL implementation skills and Data Communication Protocol knowledge are demanded.

Summary
More than 4 years of extensive experience in ASIC/FPGA design engineer having the proficiency in Architecture design from specification, effective RTL modeling, Functional and Timing Verification, FPGA Prototyping.

Experience
Working as a Design Engineer in Vdesign Pvt Ltd , Pondicherry Since Jan 2000.

Worked as a Programmer Trainee in Software Technology Group International Ltd,
Chennai. From Mar 1999 to Dec 1999.
Skills/Tools
HDL : VHDL , Verilog
EDA Tools : Modelsim SE/EE 5.4d (Mixed simulation )
Active VHDL
Matlab
Synthesizer : Leonardo Spectrum Level-3 (Exemplar Logic)
Place & Route : Alliance/Foundation Series, MAX+plusII 10.1
ASIC : Verification using PROTOTYPING SYSTEM –VRAP
Languages : C,BASIC JAVA
Scripting : perl
Operating System : DOS, Windows NT/98

Knowledge Base
CDMA, JTAG, ATM, CMOS Concepts, VITAL Simulation, Blue-Tooth, Reconfigurable Computing, DFT, FPGA architecture and Microprocessor Design

Educational Qualification

Qualification : B.E (Electrical and Electronics Engineering)
Aggregate Marks : 64%
Year Of Passing : 1998
University : Barathidasan University (1994-1998)
College : J J College of Engg & Tech

Project 1
Current Involved:

Project Name : VRAP TESTING (VDESIGN RAPID ASIC PROTOTYPING)

Project Description : RAPID ASIC PROTOTYPING makes use of re programmable FPGA chips for logic validation. The user's logic is loaded onto programmable logic and extra memory chips are added along with the logic to validate the vectors. At this point of time, the behavioral simulation is more attractive as it helps to do regression test and validate the concept.
Project Duration : Jun 2002 to till date
Team Size : 1
Role : I had my own part in VRAP functional testing .I have done Verilog and VHDL models to verify its functionality. In specific, I have designed SDRAM Emulator (1GB module) core in VHDL. This core is being used to validate VRAP functionality.
Technologies used : XILINX/ALTERA
Languages : Verilog and VHDL
Tools : Modelsim SE/EE 5.4d (Mixed simulation ),
Leonardo Spectrum Level-3 (Exemplar Logic)
Alliance/Foundation Series, MAX+plusII 10.1
Operating system : Windows NT/98
Hardware : Verification using PROTOTYPING SYSTEM –VRAP
Client : VDESIGN PVT LTD

Project 2

Project Name : Boundary Scan Architecture

Project Duration : Dec 2001 to May 2002
Team Size : 3
Project Description:
BST is a method for testing boards using four-wire interface. It provides a standard means of communicating with test circuits on-board an ASIC. Boundary Scan is the application of a scan path at the boundary of IC’s to provide controllability and observability access via scan operations. The scan path consists of a series of Boundary scan cells. These cells in a device can force signals onto pins or capture data from pin or core logic signals. Forced data is serially shifted into BSC’s. Captured data is serially shifted out and externally compared to expected results.

Role : Designing and Testing
Technologies used : XILINX
Languages : VHDL

Project 3

Project Name : CODEC

Project Duration : Oct 2001 to Dec 2001.
Team Size : 1
Project Description : Codec using micro-law
The designed Codec will provide high performance solutions for a broad range of applications requiring speech compression and decompression. A codec is designed with a Coder and a Decoder. A Coder compresses the 14-bit data input to 8-bit data output. A Decoder decompresses the 8-bit data input to 14-bit data output. A synthesizable VHDL model is written.

Role : Designing and Testing
Technologies used : XILINX
Languages : VHDL

Project 4

Project Name : Synthesizable VHDL model of ATM Switch

Project Duration : May 2001 to Oct 2001
Team Size : 2
Project Description : ATM switch is used in packet switching network. The topology used here is Batcher-Banyan. The switch can support both unicasting and multicasting. The speed of operation of the switch is 51.84 MHz.The project simulation time was in hours , which was validated using Vdesign’s proprietary VRAP tool. The verification time was cut down by a factor of several days, if the same simulation was carried out by software tool only.

Role : Designing and Testing
Technologies used : XILINX / ALTERA
Languages : VHDL

Project 5

Project Name : Universal Asynchronous Receiver Transmitter
Project Duration : Feb 2001 to April 2001
Team Size : 1
Project Description : The UART consists of three modules the transmitter and the receiver, baud rate controller. These modules are combined at the top level of the design. Data can be written to the transmitter and read out from the receiver, all through a single 8 bit bi-directional CPU interface. Both modules share a common master clock. Within Each module, clk is divided down to independent baud rate clocks.

Role : Designing and Testing
Technologies used : XILINX / ALTERA
Languages : Verilog and VHDL

project 6

Project Name V20K and U50K FPGA Development platforms.
Project Duration : Sep 2000 to Jan 2001
Team Size : 1
Project Description : Designed and developed Universal FPGA Development platforms with support for VHDL and VERILOG code. VHDL/Verilog code based designs can be downloaded and outputs can be verified through LED and LCD monitors. Coded programs for LED and LCD(Control and Sequencer Block) using VHDL. Analyzed units were synthesized using Leonardo spectrum targeting to XILINX Spartan FPGA. Downloaded designs to FPGA chip using Design manager. Tested and verified actual performance of code on LCD monitor after checking correct outputs in Modelsim. Checked for modules overcoming time constraints using Static Timing Analyzer.

Role : Designing and Testing
Technologies used : XILINX
Languages : VHDL

Project 7

Project Name MOTOR CONTROLLER
Project Duration : May 2000 to Aug 2000
Team Size : 2
Project Description : This project is basically developed for DC motor control application. The current and Temperature of the motor were measured in real-time and the speed of the motor was controlled using PWM.

Role : Designing and Testing
Technologies used : XILINX
Languages : VHDL

Project 8

Project Name :EMBEDDED CONTROLLER

Project Duration : Jan 2000 to Apr 2000
Team Size : 2
Project Description : Process controller consists of a microprocessor, which is the heart and has input interface (keypad, key scanner) & output interface (display unit). Processor consists components such as Multiplexer, Program Counter, Register, Instruction decoder, Arithmetic and Logic Unit (ALU), Memory (RAM and ROM) and Timing Control Unit (TIM). The process controller was used to control the industrial relay boards. Microprocessor is interfaced with TIMER,A/D and PIO for various controlling applications.

Role : Designing and Testing
Technologies used : XILINX
Languages : VHDL

Personal Details

DOB : 10- 06 -1976
Marital Status : Single
Passport No. : B2088401.
Current Salary : 8000 per month
Current employer : VDESIGN Pvt Ltd
Total annual gross salary : 96000/-
Notice period : 15 days
Time Required To Join : 20 days
Total experience : 4 years
VLSI Experience : 3 years
Current location : Bangalore
Willingness to relocate to Bangalore : yes or any where
evening telephone numbers : 080-5247168

Reference

1.UMA MAHESWARI
Lead Engineer
HCL TECHNOLOGIES LTD.
Chennai-26
Email: uviswana@cisco.com
Tel:044-23750171

2.MUNISHWARA RAJA.M
RELQ Software Pvt.Ltd.
Bangalore-560068.
Email: muniswara.rajax.muneeswaran@intel.com
Tel:9866055242