Posted by on February 13, 19103 at 21:09:35:

PREETHAM.RAVI
S/o R.Babu Rao
D.No: 33-23-25/3
Krishna Rao Street
Kasturibaipet
VIJAYAWADA-520 010

Tel.No: 91-866-2434502 Email: preetham_raavi @yahoo.com

CAREER OBJECTIVE:
Looking for a challenging career, which demands the best of my professional abilities, technical and analytical skills. A job which will help me in upgrading my current skills and knowledge and where I can have a good scope for learning and implementing new technologies.

SKILL SETS:
Hardware Description Languages: Verilog HDL and VHDL.Design Flows: FPGA and ASIC.Domains: Telecom and Digital Signal Processing (DSP)

EDUCATIONAL DETAILS
Examination University/Institution Year of passing Percentage
B.Tech GITAM, Andhra University 2001 69.0
Intermediate GowthamJr.College, Vijayawada 1997 90.1
SSC Gowtham Public School,Vijayawada 1995 81.0

PROJECT EXPERIENCE
VLSI PROJECTSProject1: Title: BUS INTERFACE UNIT OF 8086 MICROPROCESSOR (presently Undergoing)Guide: Mr. GANGADHAR .K (Field Application Engineer, Xilinx Division, CG-CoreEL BANGALORE)Description: The aim of the project is to design a Bus Interface Unit of 8086 microprocessor.8086 fetches the instruction from the external RAM/ROM. This needs a handshake process involving read/write and memory select signals. It also needs to interface with other peripherals like the programmable interrupt controller and DMA controller, which expects a known behavior from the 8086.In the maximum mode, it needs to interface with co-processor .All these external interfaces have been identified and the Bus Interface Unit (BIU) takes care of these functionalities.Role: Coding for Bus Interface Unit.Project2: Title: IMPLEMENTATION OF SCAN AND ATPG ON 8031 MICRO CONTROLLER COREGuide: Ms. ASHA (Sr. Application Engineer, CG-CoreEL BANGALORE)Description: The aim of the project was to perform scan insertion on the given core, generate optimized test patterns and check for the functionality, timing issues.Role: Scan insertion on the given netlist of 8031 microcontroller.Tools used: DFT Advisor, Fast Scan, Formal Pro, SST Velocity.Project 3: Title: CRC GENERATOR AND CHECKER`Guide: Mr. K.S.CHETHAN (Sr. Design Engineer, CG-CoreEL BANGALORE)Description: The CRC performs a mathematical calculation on a block of data and returns information (number) about the contents and organization of that data. So the resultant number uniquely identifies that block of data. This unique number can be used to check the validity of data or to compare two blocks. So this approach is used in many communication and computer systems to ensure the validity of the transmitted or stored data.Role: Coding of CRC Generator and testing.Tools used: Modelsim, Leonardo Spectrum, Xilinx Project Navigator.Project 4: Title: FULL CUSTOM DESIGN OF 32 BIT RIPPLE CARRY ADDERGuide: Mr. K.S.CHETHAN (Sr. Design Engineer, CG-CoreEL BANGALORE).Description: The aim of the project was to design a 32-bit ripple carry adder using the standard cells NAND, NOR, INVERTER. Estimation of propagation delay, noise margin, fan out, power. Layout was drawn, checked for DRC, extracted the parasitics, timing simulation was performed taking parasitics into consideration.Role: Drawn the layout, checked for DRC.Tools used: IC Station, Calibre, Xcalibre, Eldo.Project 5: Title: TRAFFIC SIGNAL CONTROLLERGuide: Mr. Sunil Joshi (Product Manager, CG-CoreEL BANGALORE)Description: The aim of the project was to design a Traffic Signal Controller that controls the flow of traffic as per the given specifications. Following steps were performed: RTL coding (in Verilog) – the design was divided into smaller blocks in each case; Functional verification with test bench. Synthesis – an EDIF net list was generated; subsequently Placement and Routing were done.Role: Coding of Traffic Signal Controller.Tools used: Modelsim, Leonardo Spectrum, Xilinx Project Navigator.Academic Project:Title: Realization of Data Acquisition CardGuide: Prof.P.Ramesh (Head of the Dept., EIE, GITAM, Visakhapatnam)Description: Data Acquisition, by definition is acquiring the analog dataand storing it in memory device. Since analog data cannot be stored, it can be converted to digital data and stored for further analysis of original signal. The main functions of Data Acquisition Card are----a) Conversion of physical parameters into varying signals.b) Conversion of analog signals into digital signals.c) Interfacing of digital signals to computer terminals.Data Acquisition Card is used to measure and record analog signals in basically two different ways----a) Signals that originate from direct measurement of electrical quantities. These signals may be a DC or AC voltages, frequency or resistance, etc.b) Signals that originate from the use of transducers. The aim of the project is to design and construct a Data Acquisition Card. The software is developed in Intel 8086 microprocessor assembly language.The circuit diagram of Data Acquisition Card consist of sample and hold (SH) circuit—AD 585,an A/D converter—AD 574 A, a parallel programmable interface (PPI)—8255A,and the address decoding logic.Role: Designed using Smart software, assembled, tested for output.

TECHNICAL SKILLS
DIGITAL ASIC BACKENDMOS Transistor theory. Basic Combinational Circuits, Pass Transistor Logic & Transmission gates, Dynamic logic circuits, Physical design/layoutHDL Languages· Verilog HDLLanguage concepts, constructs, coding for synthesis, verificationCase Study: Digital Alarm Clock.Environment: OS: Windows NT, Simulation tool: ModelSim, Compiler: VC++· VHDLLanguage concepts, constructs, coding for simulation & synthesis, Test benchDesign.Case Study: FIFOFPGA DESIGN MethodologyIntroduction to Programmable Logic, Xilinx FPGA Families, Design Methodology, Design entry, Verification, Synthesis, Backend Tool- Xilinx design Manager., Configuration modes.Design Implementation using Xilinx demo board.EDA TOOLSMentor GraphicsFront End Tools – HDL Designer Series, ModelSim Simulation Tool, Leonardo Spectrum Synthesis Tool, Formal Pro, SST Velocity.Digital ASIC Back End Tool – IC Station, Calibre, Xcalibre.Analog Design Simulation – Eldo, Advance MS.Design For Testability: DFT Advisor, Fast Scan, Flex Test, MBIST Architect,BSD Architect.Trans EDAVerification Navigator 2002.05 – VN-Control, VN-Property DX, VN-Cover,VN-Optimize, VN-Check.XilinxXilinx ISE – 5: Project Navigator 5.1iDOMAIN KNOWLEDGETELECOMIntroduction to Telephony, E1, E3, T1& T3 Framers, Wireless Communications.DSPSignals & Systems, Z Transforms, Spectrum Analysis – DFT, FFT,Digital Filters - IIR, FIR.PROJECT MANAGEMENTDesign Specifications, RTL Design & Documentation, Test bench Design and Documentation, Coding and Verification, Synthesis Report, P & R Report.EXPOSURE TO WINDOWS NT AND SUN SOLARIS PLATFORM

AREAS OF INTEREST
RTL CODING, VERIFICATION & TESTING, FRONTEND & BACKEND DESIGN.

TRAINING PROGRAMS ATTENDED
PG Diploma Program in VLSI Design – Sandeepani School of VLSI Design – A Training Division of M/s. CG-CoreEL Programmable Solutions (P) Ltd. Bangalore.

SELF EVALUATION
· Highly motivated and self-confident person with high level of optimism.· Good Communications skills, Goal oriented.

ACHIEVEMENTS
· Participated In Seminar on “Security Measures Using Digital Signatures” and stood second.· Received scholarship on merit until engineering from State Bank of India, Vijayawada.

References:
1. K. ANANDARAM Sr. IC Design Engineer, Semi Con. Division, SASKEN COMMUNICATIONS Bangalore. 2. K.S.CHETHAN Sr.Design Engineer, CG-CoreEl Programmable Solutions Pvt.Ltd. Bangalore. Ph. 91-080-5529733/34.