Posted by on December 09, 19102 at 13:46:46:

Resume Manjesh J.C.

Career Objective

Taking up a challenging job that encourages constant learning and
innovative skills and ensures exposure to evolving technologies.

Education From 1996 - 2000

Bachelor of Engineering in Electronics & Communications (Class1 with Distinction)
S.J.C.I.T. Chickballpur.

Skill Set

Digital Design using VHDL, Coding, Debugging using Xilinx FPGA and CYPRESS CPLD.

Domain Knowledge

VHDL, C.
Assembly language of the 8085 processor.

Hardware Skill set

Hardware Debugging of FPGA and CPLDs
Board level Design
Microprocessors

Software Skill set

Languages VHDL, C.
OS windows9x
Processors Intel 8085,8086,80960.
Tools Xlinx F4.1I, Cypress Warp, Active HDL Simulator, Max plus2 , Quartus (Altera) ,Model Sim, and Cadence Leapfrog simulator, Orcad 9.
Protocols None

Professional Experience

Mr. Manjesh JC has worked in Digital design and development for 3 years. The majority of the projects that he has undertaken have been carried out in VHDL.

1. Designing datapath components in VHDL, verifying them to be consistent with the processor description data sheets, integration of components.

2.Designing test benches and verifying them against the synthesized processor design.

3.Use of VLSI synthesis tools for ASIC design and test/verification.

4.Preparation and presentation of test and design results

5. Documentation and customer support.

Projects

Aug 2002 till date
Job Title –Senior Design Engineer
Team Strength – 3
Design of the VME 64 Bus controller

Client: VP technologies Atlanta U.S.A.

The VME64 specification establishes a framework for 8-, 16-, 32, and 64-bit parallel- computer architectures that can implement single and multiprocessor systems. on the VMEbus specification released by the VMEbus Manufacturers Group in August of 1982. This bus includes the initial four basic subbuses: (1) Data Transfer Bus (2) Priority interrupt bus, (3) Arbitration bus, and (4) Utility bus.

My role was the implementation of the priority interrupt bus modules viz., the interrupt Handler and the interrupters.
The VMEbus includes a Priority Interrupt Bus, which provides the signal lines needed to generate and service interrupts. Interrupters use the Priority Interrupt Bus to send interrupt requests to Interrupt Handlers, which respond to these requests.

Tools used: Altera’s QUARTUS II and MAXPLUS II, Exemplar’s LEONARDO SPECTRUM.

May 2002 -July 2002
Job Title –Senior Design Engineer
Team Strength – 6
Client: VP technologies Atlanta U.S.A.
DESIGN OF INTEL 960 SERIES OF PROCESSOR.
As Design engineer – Responsible for the design, coding and testing of Execution unit. Execution unit, which is one of the primary components of the processor, are designed, as per the specifications of 960 processor. My contribution to the project was thedesign of the logical, compare, and shift operations. Presently the team is working on the integration of the individual units of theProcessor.

Tools used: Altera’s QUARTUS II and MAXPLUS II, Exemplar’s LEONARDO SPECTRUM.

DEC 2001 – May 2002
Job Title –Senior Design Engineer
Team Strength – 8
Client: VP technologies Atlanta U.S.A.
The SNX 8500
The SNX 8500 is a soft network exchange supporting VOIP. This product interfaces the EPABX with the existing LAN, so as to enable conferring via LAN.

DESIGNING OF Glue logic for the SNX 8500
Designed the glue logic for the Analog line card, Digital line card, analog trunk card
And the piggy back card. Tested the functional and timing simulation using the warp 6.0
Tool from Cypress. It was then downloaded on to a the pi -Board through JTAG
Cable and was tested.

RESPONSIBILTIES

As a Team member, Designed and Implemented VHDL module:
Collected the Requirements and Designed the PFS generator clock divider and associated
Control logic.

SEP 2001 –DEC 2001
Job Title – Design Engineer
Team Strength – 8

Board level design of the DC to DC converter for the SNX 8500.
Board level design of the DC to DC converter, which will be used as a power supply for the telephone buzzer. The conversion was an input of –48v dc to 100v dc

RESPONSIBILITIES
PCB layout using Orcad, component assembly and testing.

MAY 2001 _ AUG 2001
Job Title – Design Engineer
Team Strength – 3
Client: VP technologies Atlanta U.S.A.
INTEL 8259 PRIORITY INTERRUPT CONTROLLER: This is a generic and synthesizable VHDL module. The core is designed and implemented to relieve the system CPU from the task of polling in a multi-level priority interrupt system. The 8259a can handle up to 8 vectored priority interrupts for the CPU and is cascadable to 64 interrupts without additional circuitry. It is designed to minimize the software and real time overhead in handling multi-level priority interrupts.

RESPONSIBILITIES:
As a Design Engineer, Designed and Implemented VHDL module for the Slave INTEL 8259 Interrupt Controller. I was also involved in Carrying out the Unit and Integration testing.

Software Used – WARP 6.1

Nov 2000 _ APR 2001
Job Title – Design Engineer
Team Strength – 3
Client: BPL Telecom Limited Bangalore
MT 8952B HDLC CONTROLLER: The MT8952B HDLC PROTOCOL CONTROLLER handles bit oriented protocol structure and formats the data as per the packet switching protocol structure defined in the X.25 (Level 2) recommendations of the CCITT. It transmits and receives the packeted data (information or control) serially, while providing the data transparency by zero insertion and deletion. It generates and detects the flags, various link channel states and the abort sequence. Further, it provides a cyclic redundancy check on the data packets using the CCITT defined polynomial. In addition, it can generate and detect a Go Ahead sequence and recognize a single byte address in the received frame

RESPONSIBILITIES:
As. Design Engineer, Designed and Implemented VHDL "RECIEVER" module which comes in the Receiver section of the MT 8952B HDLC CONTROLLER. Collected the Requirements and designed the blocks, integrated all the blocks Coded extensively, carried out Unit and Integration testing.

Software Used – WARP 6.1

Nov 1999 – Aug 2000
Job Title – Project Trainee
Team Strength – 4
Academic project @ BPL Telecom Limited Bangalore
DESIGNING AND IMPLEMENTAION OF CACHE MEMORY CONTROLLER
The cache memory controller is an interface between the cache memory and the
Main memory The Controller reduces the delay of the data flow between the main
Memory and the processor. This uses the block set associative method of data
Association between the main memory and the cache memory and uses the LRU
(Least recently used) algorithm to replace the blocks that are not frequently used

TOOL: CADENCE LEAPFROG SIMULATOR

RESPONSIBILITIES:
As a Team member, Designed and Implemented VHDL module:
Collected the Requirements and Designed the Mapping function between the main
Memory and the cache memory · Coded extensively carried out Unit and Integration
Testing.

Personal Information
Name : Manjesh JC
D.O.B. : 19-09-1978.
Address : #1084, 7th Block, 8th Cross, H.M.T. Layout
Vidyaranyapura. Bangalore 560097.
Ph 6589080-89 ext 2101(off)
3641035 (res.)
E-mail: jcmanjesh@yahoo.co.in
manjesh.jc@bplmail.com