VLSI / ASIC / Digital Design Engineer

VLSI / ASIC / Digital Design Engineer


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Posted by on November 25, 19102 at 15:47:22:

Curriculum Vitae’


Nikhil P. Parekh
1/39 Udgognagar Co-op Hsg.Society,
Post: Mogari. Dist: Anand Phoe No. : 02692-238860
Gujarat - 388345 India. E-mail : nikparekh@yahoo.com


OBJECTIVE
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To seek the suitable opportunity where by utilizing my skills and knowledge gained in the engineering & technological areas and can excel the generic technologies in the engineering field for the growth of the industry and reach the level of self-actualization.

WORK EXPERINCE
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Worked as a lecturer at Sarvajanik College of Engineering and Technology, Surat-Gujarat in Electronics Engineering Dept. from August-2000 to February-2002.

Worked as an Engineer at Elecon Engineering Co. Ltd, V.V Nagar –Gujarat in Electronics dept. from August 1999 to August 2000.


EDUCATION
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Diploma in VLSI Design from C-DAC, ACTS, Hyderabad
Stood FIRST
Module consists of Advance Digital Design, VHDL, Verilog, CMOS VLSI Design, System Architecture, FPGA.

B.E. (Electronics)
South Gujarat University, Surat, Gujarat
Studied Mobile Communication & Satellite Communication as an elective subject (GSM, TDMA).
Studied courses on Electronic System Design.
Very good knowledge of 8085 Assembly language Programming


ACADEMIC RECORDS
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Bachelor of Engineering 77 %
Diploma in Electronics & Communication Engg. 81 %
Diploma in Electrical Engg. 72 %
H.S.C. 63 %
S.S.C. 75 %


SKILLS SUMMERY
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Operating System :MS-DoS, Windows NT, Windows XX
Languages :VHDL, Verilog, C

EDA Tools
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Simulation :ModelSim SE 5.5C, IRSIM, Spice.
Layout Tools :Magic, Alliance.
Synthesis Tools :Leonardo Spectrum
Place & Route Tool :Xilinx Design Manager
FPGA Download :Xilinx 3000, Xilinx 4000E


PROJECT
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# Microprocessor Based Temperature Controller - During B.E (Final Year).
# USB Host Controller and HUB - During D-VLSI Design.
# Morse Decoder in VHDL (Mini Project).
# UART in Verilog and VHDL.

SEMINAR
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Spread Spectrum Modulation.


INDUSTRIAL TRAINING
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@ TATA Telecom Limited, Gandhinagar - 3 Months.
@ Power Build Limited, V. V. Nagar - 2 Months.

STREANGTHS
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Time management skills
Dynamic team player
Sense of responsibility
Excellent skills in communication
Creative and resourceful



PERSONAL DETAILS
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Name :Nikhil Parsotambhai Parekh

Permanent Address :1/39, Udyognagar Co-Op.Housing Society,
Opp: “ITC”,
Post: Mogari,
Dist: Anand – Gujarat
388345 – India.

Phone No. :(R) 02692-38860

Email :nikparekh@yahoo.com

Marital Status :Unmarried

Date of Birth :19 August 1974

Nationality :Indian


REFERENCE
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Dr. N. Sarat Chandra Babu Prof. Niteen B. Patel
Programme Coordinator, Head, Electronics Engineering Dept,
C-DAC, ACTS, Sarvajanik College of Engg. & Tech.
Delta Chambers, Ameerpet, Athawalines,
Hyderabad-500016 Surat. 395001

Sincerely Yours,


Nikhil P. Parekh


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