Posted by on November 01, 19102 at 23:18:18:

NAME :Venkata Raghavan.S.
Date of Birth :22-05-1968
Education :Bachelor Of Engineering in E& CE
Pre –University :Karnataka board
S.S.L.C :Karnataka board
University :Gulbarga Univeristy , Karnataka state , INDIA
Year of pass out :1990
Mail id :swayamv@yahoo.com
Phone :+0091-080-8511276

Objective: Work for cutting edge Technology with dedication.

Skill Sets:
· Project management and business development for the customer based projects
· Project Planning and execution with team .
· Digital System Design .
· Microprocessor based system design.
· ASIC front end coding , verification and prototyping with FPGA
· EPLD , FPGA based designs for cutomer needs
· High speed PCB designs with signal integrity analysis
· Mixed signal Board design
· Knowledge of the Networking protocols and ATM
· Embedded system (Network processor ).
· RF design

Experience :

Deccanet Designs Limited: Bnagalore.
Period of service : From Jan '02 till Date .
Designation: Technical Manager
Role and Responisibilities:
· Head the hardware design team for project execution .
· Business development for Embedded systems and hardware projects for both National markets and international bidding .
· Key design and Architecting for the customer projects .
· Lead a team size 0f 20 talented engineers .
· Planning and Road map of the products and services .

Projects Handled:
· 4Line VOIP pbx for Small office Home office applications
· Standalone system with 4 Telephone connections and Ethernet support .Egress traffic with ADSL port supporting full rate and G.lite standards .
· Customer :ANALOG DEVICES (USA).
· Multiple services Access platform system .Backplane based design with PCI bus interfaces for terminating primary interfaces such as E1/T1 , E3/T3 , OC-3 interfaces and LAN support .Egress traffic with OC-12 and OC-48 interfaces .
· Design of Primary Mux for voice and Data transmission on 2Mb link.
· Architecture of the Edge Router System and design .

Wipro technologies :Bangalore
Period of Service : july 2000 to oct 2001 .
Designation :Project Manager
Role and responsibility:
· Lead a team of size 6 people for project execution
· Project planning and co-ordination with the customer
· Architecting and execution of the same with the project engineers .
· Project Scoping for the new customer requirements and specifications .

Projects Handled :
1. ASIC prototyping Board for MultiMillion gate ASIC with VIRTEX-E FPGA 's and analog circuits .
· The idea is to reduce the verification time of the ASIC development with the true interfaces test from the RTL fitted in the FPGA .
· certify tool from synplicity for automated way of partitioning the high level RTL in to sub modules to fit into FPGA's .The board has the debugging ports for Logic Analyzer , JTAG and test points for CRO test points and trigger .
· Its a 16 Layer board with controlled impedence .The design completed and tested at customer location .

Customer : Space Bridge Networks CANADA .

2. Signal integrity Analysis for Networking processor board .
· Pre and post routing signal integrity analysis for the Networking processor with IBIS models .
· The processor is complex one with interfaces such as 10G bit ethernet port , SDRAM port , PCI port and switch fabric interface.The data rate at the switch fabric port will be 200 Mbytes /sec.
· The complete solution for the High frequency board design is provided .

customer:EZ CHIP TECHNOLOGIES , ISRAEL

3. Evaluation of RTL for Bluetooth ASIC :
· Providing a Prototyping platform with FPGA based board and ARM7TDMI processor .XCV1000E device with the processor and flash , sdram and sram for envisaging the complete system .
· The ASIC is for handling the baseband processing of Bluetooth ver1.1 .The proto board will evaluate the co-verification exercise to reduce the time of the verification and also provide the real time testing which can be used even for the field trial before the tapeout of the Silicon .
· The base band Module is completely tested at the customer site at the rate of 2Mbits /sec and the interface with the RF module is established .
customer :Alacatel , BELGIUM .

4 Productivity drive and scripts :

· Involved in the tools automation in the board design cycle for quality improvement and also reduction of the cycle time .
· Scripts are developed to have a patch with the tools for schematic capture and PCB routing , verification and signal integrity .
· The scripts developed with team of engineers with PERL

5. Training session for project Engineers :
· Conducted training and seminars for the board design concepts , signal integrity and Logic synthesis and design .

Indian space research Organization :Space Application Centre , AHMEDABAD .
Designation :Scientist/Engineer - SD.
Period :june 1992 to july 2000 .
Projects Handled :
· Data interface units for IRS-1C payload camera
· Frame synchronizer and Decommutator unit for INSAT camera payloads
· Real time Data acquisition system , standalone to transfer data at 50 Mwords / sec for 100 Mbytes storage .
· PCI based data acquisition cards for real time transfers of image data .
· Device driver development for the PCI , ISA cards along with the system design .
· Design of the complete sub systems based on the CPLD from ALTERA or FPGA from the XILINX .
· Complete cycle of design , schematic capture and board routing for the high speed boards .

Tools Known :
· Orcad and Concept for schematic capture
· Allegro from CADENCE for pcb routing .Spectra for auto routing
· Quad XNS from innoveda for signal integrity analysis.
· Synplify pro for synthesis M1 tool for place and route.
· Xilinx foundation series ALTERA Maxplus -ii for CPLD design and development .

Extracurricular activities :
· Radio ham with grade -1 licence
· Built HF/VHF transcivers for ham bands .