Posted by on October 30, 19102 at 06:23:41:

MAHESH INDRAN

854 E, Adams Street, indran@email.arizona.edu
Tucson, AZ 85719. Tel. no: (520) - 792- 2618

OBJECTIVE: Seeking a full time position that offers challenging opportunities in the field of ASIC /
VLSI / Digital Hardware Design.

EDUCATION:
MS, Electrical & Computer Engineering Aug 2001 - Present
University of Arizona. (GPA: 3.375) (Expected: Dec 2002)
BE, Electronics & Communication Engineering 1996 - 2000
Bharathiyar University. (GPA: 3.94)
Cumulative GPA: 3.65 / 4.0

TECHNICAL SKILLS:
PROGRAMMING : Verilog HDL, Spice,C, ORACLE,VB, FORTRAN.
PACKAGES : PSpice, MAGIC
OPERATING SYSTEMS : Windows 95/98/NT/2000, LINUX.
PLATFORMS : SUN SOLARIS, MACINTOSH and PC’s.
WEB SKILLS : HTML, JAVA 2.0.
CURRENT EMPLOYMENT:
Teaching Assistant for ECE 369 (Computer Architecture) Jan02 - Dec02
Topics include: Fundamentals of computer architecture and organization, including the CPU, memory, registers, arithmetic unit, control unit, and input/output components, RISC architectures, interface between assembly and high level language programming constructs and hardware, instruction and memory cache systems, performance evaluation, benchmarks.

WORK EXPERIENCE:
ASIC DESIGN ENGINEER, C-Logic India, Coimbatore,India June 00 - June 01
Co – Op Engineer, C-Logic India, Coimbatore, India Aug 99 – May 00
PROJECTS :
Verification of an ASIC Interface Chip between Fiber Channel and Gigabit Ethernet.
LANGUAGE: Verilog HDL.TOOLS: Finsim, Sledge Hammer, SynaptiCAD Verilogger Pro.

Synthesizeable controller for SRAM (K6T4016c3B).
LANGUAGE: Verilog HDL. TOOLS: Xilinx FPGA Express,SynaptiCAD Verilogger Pro.

IrDA – IrLAP.
Design handles protocol layer.
LANGUAGE: Verilog HDL. TOOLS: SledgeHammer, SynaptiCAD Verilogger Pro

ACADEMIC PROJECTS:
Error Detection and Correction Chip – CMOS Design and Chip Layout Jan02-May02
TOOLS: PSpice, Spice, MAGIC

Universal Serial Bus Interface Chip. May 99 - March00
Acts as an interface between USB 1.1 and SCSI.
LANGUAGE: Verilog HDL. TOOLS: Wellspring Solution's Veriwell, SynaptiCAD Verilogger Pro.

TECHNICAL PRESENTATIONS:
"Serial Interface Engine for USB".
Designed using Verilog HDL.
Won Second Prize at All India Technical Symposium-VISION 2000.
"Leading Zero Detector".
Algorithm- Coding in Verilog HDL.
Won Second Prize at All India Technical Symposium- Techfiesta 2000.
Won Second Prize at All India Technical Symposium- VISION 1999.

HONORS:
President - DIGITALK 2000 - A National Level Technical Symposium for Electrical Engineers, India.

REFERENCES: Available upon Request.
MISCELLANEOUS: Willing to Relocate.