Posted by on October 29, 19102 at 15:01:04:

Email: senthil_ece2000@yahoo.com Address:
E.Muthulingapuram
Naduvappatti-post,
Phone: 91-4562-356752 Sattur-taluka,
Tamilnadu-626203.

Objective: Seeking a challenging environment in IT industry which
involves in VLSI / ASIC design and development in order to assist your
organization in achieving it's goal.

Educational Qualifications:

* Diploma in Backend Digital ASIC Design Engineering, ATIIT Pvt. Ltd,
Chennai.
(June 2000 - August 2000).
* B.E. in Electronics & Communications from Mepco Schlenk Engineering
College, Sivakasi, India.
(1996 - 2000). 69.1% overall. Passed in first class.

Professional Experience:
Two years in VLSI Design
* DARIEN ELECTRIC (P) LTD., CHENNAI
Jan 2002- Till Date
Member Technical Staff
* AVANTI SOFTWARE AND DEVELOPMENT CENTRE (INDIA) PVT. LTD. Sept 2000 -
Nov2001
Design Engineer

Software Proficiency:
* Languages: Verilog HDL and C
* Operating Systems: Windows NT/9X/2000, MS-DOS, HP- Unix
* Protocols: PCI 2.1, IEEE 1394, HDLC
* Expert Training: VLSI Backend Design using Mentor Graphics, Avanti
* Packages: MATLAB 5.3 (DIP, Neural Networks), Aphelion and Adobe
Photoshop

EDA Tools for Front-end:
* Simulators: Polaris and ModelsimEE
* RTL analysis: Explore RTL
* Synthesis: Leonardo Spectrum
* Formal Verification: Design Verifyer
* Real time projects: PCI generic core, IEEE 1394 Interface.

EDA Tools for Back-end:
* Data preparation: Milkyway
* Place & Route: Apollo, Mentor Graphics Calibre
* Timing Analysis: Saturn
* FPGA tool: Xilinx.
* Real time projects: Exhaustive Benchmarks implemented on Area
optimization and
timing optimization.
Projects:
Front end: PCI generic core, IEEE 1394 Interface, HDLC Core,
16Bit ALU and FIFO Backend : Benchmark 1
(Area Optimization), Benchmark 2 (Timing Optimization)
Training projects : 16 Bit Square root design, Multiplier
Academic Project: Face Recognition Using Neural
Networks & Digital Image Processing.
PROJECT 1: HDLC CORE
DARIEN ELECTRIC (P) Ltd
Duration: Six months Team Size: One
HDL: Verilog
Tools: ModelsimEE, Leonardo Spectrum

Overview : HDLC stands for High level Data Link Layer. It's
functionality essentially involves in framing the data in HDLC frame format. The
HDLC framed data will be transmitted / received through the 32
different time slots. It supports both transmit and receive as well as full
duplex mode of operation. It ensures the data integrity through the 32 bit
CRC. The core is designed to operate in 66 MHz. It finds application in
telephony, Fax, VoIP, etc.
Responsibilities:
* RTL Coding and functional verification, RTL Analysis and Synthesis

PROJECT 2: 16BIT ALU DES IGN
DARIEN ELECTRIC (P) Ltd

Duration: One months Team Size: One
HDL: Verilog
Tools: ModelsimEE, Leonardo Spectrum

Overview: This is the area of microprocessor where the various
computing functions are performed on the data. The ALU unit performs arithmetic
operations such as addition, subtraction, multiplication and division
and the logical operations such as And, Or, Nand, Nor, Xor and Xnor.
Responsibilities:
* RTL Coding and functional verification,RTL Analysis

PROJECT 3: PCI v2.1 Generic Core
AVANTI
Duration: Five months Team Size: One
HDL: Verilog
Tools: Polaris, Explore RTL.
Overview: The PCI Local Bus is a high performance 32/64-bit bus with
multiplexed address and data lines. The bus is intended for an
interconnect mechanism between highly integrated peripheral controller
components, peripheral add-in boards, and processor/memory systems. Fully
compliant with PCI Special Interest Group (PCI_SIG) PCI Local Bus
Specification, Revision 2.1
Responsibilities:
* RTL Coding and functional verification,RTL Analysis

PROJECT 4: IEEE 1394 FIREWIRE SYSTEM
ARCHITECTURE AVANTI
Duration: Three months Team Size: Four
HDL: Verilog
Tools: Polaris, Explore RTL.
Overview: This project provides IEEE 1394 PHY layer digital core with
an adaptability of Beta mode, DS mode and link layer interfaces. The
digital core was designed such that it can support multiple ports.
Responsibilities:
* RTL Coding and functional verification,RTL Analysis

PROJECT 5: BENCHMARK 1 (AREA OPTIMIZATION)
AVANTI
Duration: Two months Team Size: One
Tools: Milkyway, Apollo, Saturn
Overview: The area is optimized through the proper constraints set in
the data preparation and Floor planning.
Responsibilities:
* Data preparation,Floor planning, Place & Route.

PROJECTS 6: BENCHMARK 2 (TIMING
OPTIMIZATION) AVANTI
Duration: Two months Team Size: One
Tools: Milkyway, Apollo, Saturn

Overview: The interconnect and intrinsic delays are optimized during
the Inplacement, Clock Tree Synthesis and Interactive optimization.
Responsibilities:
* Data preparation,Floor planning, Place & Route. Static Timing
Analysis