Posted by on July 31, 19102 at 16:53:44:

R E S U M E
NISHANT KULKARNI

Name of Father : Dattatraya Kulkarni
Date of Birth : 25th September 1979.
Sex : Male
Nationality : Indian
Address : 93A, 20th B-Main Road, 1st R-Block,
Rajajinagar, Bangalore-560010
Qualification : B. E. Electronics & Communication.
E-mail : callnishi@rediffmail.com
Phone Number : 080-3328653 PP
Interest/s : VLSI Design (ASIC & FPGA)
Educational Details :

Degree Institute
B.E.
Electronics & communication. Kalpataru Institute of Technology,
Tiptur-572202 (Karnataka).
Semester Details
Semester Percentage
1 62.00%
2 64.70%
3 62.90%
4 71.40%
5 62.90%
6 70.40%
7 69.30%
8 78.00%
Experience : In Cisco Systems at the time of Project in below fields
5 Months on RTL Coding using VHDL & Verilog and synthesis.
5 Months on Design For Test (DFT) in ASIC and ASIC design .

Skills : Hardware Design ( ASIC & FPGA)
VLSI Design : RTL Coding using VHDL & Verilog. Synthesis,
Floor Planning, Place & Route, Timing Verification etc.
Worked on ASICs & FPGAs design. Design For Test of ASICs using commercial EDA Tools.
Computer Networks : Network Administration, Firewall architecture
Digital Signal Processing : MATLAB, Simulink.
Assembly Languages : 8085,8086,8051,68HC11.
Micro controllers : 8051, Motorola Micro controllers.
Software Programming : C, C++, and Perl 5.0 .
Operating Systems : Windows 98/ 2000/NT, Linux, Sun Solaris.

Project Details: -
Project Work-I
Title of the project: -
DESIGN OF ROUND ROBIN ARBITER USING VHDL FOR MULTISTAGE SWITCHING SYSTEMS.
Carried out at: -
Cisco Systems (India) Pvt. Ltd, Bangalore-5600025.
Project Duration : 5 Months
Under the guidance of:
1. Mr. Shriharsha balan. 2. Mr. M.Suresh
Hardware Engineer, Assistant Professor.
Cisco Systems Ltd, Kalpataru Institute of Technology,
Bangalore-560025. Tiptur-572202.
Number Of Person/s carried out the Project: - 2

Details: -
Networks are to operate as fast as possible similarly the switches and routers also have to perform at faster rates so that the information is not lost due to the delay present in the networks and switches.
We tried hard to design the controller RRA (‘Round Robin arbiter’) of these switches using VHDL so that they can perform at much more faster rates and accuracy.
At the initial level we tried to design the RRA for three-port switch i.e. only 2 bit address in RRA we can control 8 terminals. By extending the bits we can design RRA for a switch to control any number of I/O ports. If the numbers of ports are too large, we can use the multiplexers, which in turn reduces number of pins on RRA.

My Role In The Project:
My role in this project is RTL coding of the specified module using VHDL and synthesis of the given module “RRA”. Later I have been involved in the RTL coding of the RRA using Verilog HDL.

Project Work-II
Title of the project: -
MEMORY BIST AND ITS IMPLEMENTATION IN ASIC DFT
Carried out at: -
Cisco Systems (India) Pvt. Ltd, Bangalore-5600025.
Project Duration : 5 Months
Under the guidance of:
Mr. Abhijit Dutta Mr. M. Suresh
Manager – Hardware Engineering Asst. Prof., Dept. of E & C
Global Development Center Kalpataru institute of Technology
Cisco Systems (India) Private Limited Tiptur-572202, India
Bangalore – 560 027, India
Number Of Person/s carried out the Project: - 1

Details: -
The Design For Testability (DFT) is a process of adding logical circuit to ease the testability of a design circuit. DFT plays very important role in today’s ASIC test industry.
Many faults can occur in ASIC, some of them are stuck-at faults, delay faults, current faults etc. It is necessary to add a circuit to main design so as to detect these faults in order to reduce the test cost. Embedded memories are very difficult to test for faults because they are not directly accessible. Memories are highly regular structures and more sensitive to faults. The faults that may occur in memories are Stuck-At, neighborhood pattern sensitive faults, bridging faults etc. Memory BIST (Built-In-Self-Test) is the methodology of choice for testing embedded memories.
My Role In The Project:
I have generated the BIST Circuitry for various memories such as RAM, ROM. Carried out different experiments on these BISTs. The Experiments covers Sharing of these BISTs among several memories in single ASIC, Getting different test patterns to tress faults in the memories etc. After caring out all the experiment on the BIST for ASIC embedded memories I came to the conclusion that, “ Sharing BIST among all the embedded memories in an ASIC is the best method to test the embedded memories and it reduces the hardware overhead.

Yours Faithfully

Nishant Kulkarni