Posted by on July 20, 19102 at 19:25:55:

Name Mr. Kesavan Lal .L.S
Birth Date 08-09-1976
Education  B.E from Bharathiyar university in the discipline of Electronics and Communication Engineering during the year of 1999

Experience Summary  Presently Working in Larsen &Toubro InfoTech as a Team Member in ASIC Group

 Three years of experience in VLSI design, VHDL and Verilog (Hardware Description language)

 VLSI Logic Design – Complete flow from RTL design through Place & Route.

 Excellent in Verilog & VHDL Programming for RTL level Design and Verification.

 Experience as a Team Leader in Preparing Design document for the projects.

 Experience in developing synthesizable RTL codes for individual modules.

Platform OPERATING SYSTEMS
 MS-DOS
 WINDOWS 95/98, WINDOWS NT
 Unix, Linux, Vi Editor

Languages
 Verilog, VHDL.

 C, Perl.

Tools  V system VHDL tool (Mentor Graphics)
 Modelsim – HDL tool
 Verilog HDL tools (veriwell and Silos III)
 ALTERA Max-Plus II
 Leonard Spectrum –Synthesis tool
 Warp –Synthesis tool
 Speed Wave VHDL Simulator
 Orcad’s P-Spice
 Knowledge in Backend and Verification Concepts.
 Knowledge in Networking concepts

Domain / Technology Knowledge  Inter Integrated circuit bus architecture
 RTX Microcontroller
 Phase Locked Loop
 Asic Design
 Fpga Design flow
 Bluetooth
 MPEG-4.
 DCT/IDCT
 WLAN
 DSP
 VLSI Signal Processing
Experience Three Years.

Project Name 2D DCT Implementation in RTL .

Period From March 2002 – Till date.

Language Verilog

Description The scope of the design is to develop a 2DDCT(Discrete Cosine Transform) Chip using AAN algorithm for still Image compression .Pipelined architecture of 2D DCT is derived in order to achieve high speed Operation.

Contribution Currently working on the Input buffer ,Transpose memory Module.Prepared the Low level Design for the same.

Client L & T Infotech, Chennai.

Project Name Design and Implementation of FFT Processor for RDS.

Period Six Months.
Language VHDL
Client Sanyo, Japan.
Contribution Team Member,
Implemented Floating Point adder/subtractor modules, Designed Array stages of the Processor and Implemented the same. Integrated all the sub modules and Verified the same Using Mat lab.
Team Size 3,

Project Name Bluetooth – Development of Link Controller

Period Two Months
Language Verilog
Description The project is developed for L & T Infotech, India.

Bluetooth wireless technology is a standard and a specification for a small–form factor, low cost, short-range radio links between mobile PCs, mobile phones and other portables. It is used to connect computing and telecommunication devices without the need of cables. It supports rapid ad hoc connections and automatic connections between devices for synchronizing, calendars, etc. Mobile data can be used in different ways, for different applications such as cordless connection between a headset and a mobile phone, cordless transfer of files between two laptops. Mobile phone can be used for three functions: Intercom, Portable, cellular.
This project aims at the hardware implementation of the link controller.
Contribution Team member
Team size 5
During the Study phase of the project we have identified the following modules and arrived architecture for Baseband Controller. The specification from Bluetooth Spec Ver 1.0B was referred. The identified functional modules of Baseband spec is the FEC (Forward Error correction) Encoding and Decoding, HEC (Header error check) generation, Data Encryption and Decryption and CRC (Cyclic Redundancy Check) Checking & etc

Project Name Design and Implementation of Inter Integrated Circuit Bus interface
Period Five months.
Platform Unix
Language VHDL
Description
Inter IC is a simple bi-directional two wire bus for efficient inter IC control. The buses are the Serial Data Bus (SDA) and the Serial Clock Bus (SCL). Serial data bus carries information from one device to another, in synchronization with the clock in the serial clock bus. All I2C bus compatible devices incorporate an on-chip interface, which allows them to communicate directly with each other via the I2C bus.

Synthesis tools and simulation tools

V system – simulation tool, Leonardo Spectrum
Target Devcie Altera Flex 10k. Utilized 229 Logic cells
And 109 D flip flop.

Contribution Team Leader
Team size 5
Preparing Design document Implemented the Master module using VHDL and optimized the code. Tested the code by passing test vectors.

Project Name Design and Development of RTX Micro Controller

Period Six Months
Platform Unix
Languages VHDL
Description The project is developed for Apollo Laboratories, Hyderabad. This card is designed for star sensor based on Real Time Express Processor Core (RTX-2010 Micro controller). The controller card has 1553B bus interface using BU61582 BC/RT/MT has an addressing capability for 32KX8 PROM, 32KX8 RAM and BU61582. A radiation hardened FPGA based on Actel 1280CQFP device is to be designed to take care of glue logic. Further it has Universal Synchronous Receiver transmitter for data transmission through RS422 drivers and receivers. It has baud rate generator to provide a baud rate of 9600 for data transmission. The Processor is capable of operating at 12/16 MHz. The HS-RTX2010RH is a radiation –hardened 16-bit micro controller with on chip timers, an interrupt controller, a multi accumulator, and a barrel shifter. It is particularly suited for spacecraft environments, where very high-speed control tasks that requires arithmetically intensive calculations, including floating-point math to be performed in hostile space radiation environments.

Contribution Team member
Team size 5
Design of Clock generation counter, Imagezone clock generation counter, and Memoryzone clock generation counter, Line counter, Line readout clocks, Pixel counter. Tested the design blocks by passing test vectors.

Project Name Design and Development of Digital Phase Locked Loop (PLL)
Period Three months
Platform Unix
Languages Verilog

Description DPLL locks the output frequency with Input frequency and transfers the data in the locked frequency range. It compares the Input and output frequency, if they differ in frequency corresponding limit variable and output frequency is locked with Input frequency by comparing the counter value with Limit variable, only if the Input frequency lies with in the Capture range.
Contribution Team member
Team size 2
Coding in Verilog and compared the system clock and generated clock there by locking the loop. Tested by passing test vectors.

Project Name Design and Development of Arithmetic and Logic Unit for 8085 microprocessor.
Period Two Months
Platform Unix
Language Verilog
Description Central processing unit is used in calculators to perform simple arithmetic operations. In this project we have implemented arithmetic unit which is able to perform simple Arithmetic operations like Addition, Subtraction, Incrementing, Decrementing, Buffering, Inverting etc. And universal shifts register, which is able to perform operations, like SerialIn-SerialOut, SerialIn-ParallelOut, ParallelIn-SerialOut and ParallelIn-ParallelOut.
Contribution Team Member
Team size 1
Designing ALU in HDL point of view, writing code for each module
In Verilog, integrating and testing the modules.

PERSONAL PROFILE
Name L.S.KESAVAN LAL

Father's Name Mr.M.Lal Selvanayagam
Email saikesavan@rediffmail.com,kesavanlal@yahoo.com
Present Address No.52 (New), Gangaiamman Koil street,
Bharathiyar Nagar,
Chennai- 600 041
TamilNadu, South India
Permanent Address 116,N.G.G.O.’s colony,
Salamedu,
Villupuram- 605 401
TamilNadu, South India.
Employment Presently: Larsen &Toubro Infotech, Chennai
Previously: Horizon Semiconductors and Networking solutions
Pvt. Ltd., Chennai
Date of Birth 08.09.1976
Gender Male
Marital Status Single