Posted by on April 07, 19102 at 17:16:25:

RESUME
NAME : AVIRAL MITTAL

DOB : 15-Nov-1974

GENDER : MALE

MARITAL STATUS : UNMARRIED

EDUCATION : Currently pursuing MSc in VLSI Design
at Bournemouth University, UK(part time) Sponsered by
Philips Semiconductors, Southampton, England.

Degree Earned : Bachelor Of Technology (Electronics),from Institute
of Engineering & Technology LUCKNOW,INDIA(1994-1998)

PROFESSIONAL EXPERIENCE : 3+ years

CURRENT EMPLOYER : PHILIPS SEMICONDUCTORS SOUTHAMPTON UK

Sep 2000-Date : Wroking as IC Development Engineer in the Digital
Media IC Group at Philips Semiconductors Southampton UK.

CURRENT PROJECT:
Working on DFT methologies for a chip called CENTAURUS.
The task involves,study of various DFT techniques for
a system on chip ,Integration of DFT shells
and thier simulation.

PROJECTS DONE:
Behavioural Modelling for various blocks in "COBRA"
chip to be used in the CD/DVD digital audio systems
VHDL was used in the coding.(Duration 3 months)

Dec 1999-Sep 2000:MOTOROLA INDIA LTD.Worked As Design
Engineer,FRONT END.

PROJECTS DONE:
Design And Development of MUPI(Mcore Universal
Peripheral Interface)This Design is basicly
a bridge between the MCORE the microprocessor
and the peripherals connected to it.It is a highly
Parameterised design giving its user the maximum
flexibility.(Verilog was used for coding)
Duration 4 Months

June 1998-Nov 1999 STMicroelectronics NOIDA(INDIA)

Worked as Associate Design Engineer
Library Development Group,responsible for
Full Lib design starting from specs
usually in the form of a Truth Table

The develpoment procedure mainly
includes
1) CMOS DESIGN
2) LAYOUT DESIGN+DRC/LVS
3) SIMULATION OF CMOS DESIGN
4) CHARACTERISATION OF CELLS(Timing)
5) STF GENERATION
6) FRONT END MODEL GENERATION AND VALIDATION

STRENGHTS:

I)Proficiency in VHDL/Verilog coding
II)Strong background in digital logic design
III)Excellence in yhe following tools
a) Design Analyser --> SYNOPSYS
b) OPUS --> CADENCE
c) VERILOG-XL --> CADENCE
d) NCSIM --> CADENCE

EXTRA ACTIVITIES:

---> Good knowledge of Shell programming
---> Good Knowledge of Perl Scripting.
---> Fully designed and coded Intel's 8085
Microprocessor On VHDL
---> Knowledge of the 1149.1 IEEE standard for Boundary Scan
--->An Active Member of the IEEE society
---> Good knowledge of Intel's x86 Assembly Language,Architecture
---> Knowledge of PA-RISC Architecture and Assembly Language.
---> OS worked on:HP-UX,SOLARIS,WINDOWS

AREAS OF INTEREST

Digital logic design with
VHDL/Verilog coding & synthesis
timing,IP development,Microprocessors,
Assembly Language,CMOS circuit design,
ASIC design,Device Physics,Microelctronics.
DFT Implementation on SOC.

TOOLS WORKED ON:

1. Design Analyser,DC_SHELL by
SYNOPSYS -> synthesis.

2. Verilog XL for verilog

2. NCSIM by Cadence for VHDL/Verilog Sim

4. OPUS by CADENCE used for
LAYOUT DESIGN

5. SILICON ENSEMBLE by CADENCE used
for FLOORPLAN and P&R

6. ELDO by Anacad(Mentor)for circuit simulation

PERSONAL STRENGHTS:Knowledgeable,Sincere,Flexible

MAILING ADDRESS:

AVIRAL MITTAL
6,Russell Mount,
28-30 Branksomewood Road
Bournemouth
UK
Post Code:BH4 9JN

PHONE No. +44-7764369146(GSM)
+44-1202-762570(Home)
+44-23-80312561 (office)
E-Mail aviral.mittal@ieee.org , avimit@yahoo.com a1429562@bournemouth.ac.uk
WEB http://www.aviral.co.uk/

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