Posted by on October 18, 19102 at 03:37:56:

VISWANADH, KAKANI
Herman Ling Stresse4,W11
Munich,Germany 80336

Email: visu_kakani@yahoo.co.uk
visu_kakani@hotmail.com
PHONE +49-1635337344

OBJECTIVE

To obtain a challenging position in the area of VLSI Design, where my technical skills are utilized effectively and help me expand my knowledge in the field of Microelectronics.

EDUCATION

2001 - 2002
Master of Science,Electrical Engineering - Microelectronics
Birla Institute of Technology & Science, Pilani, India
* Currently working to obtain Master's Degree in Microelectronics from one of the premier institutes for Technology in India,and I will complete my Masters degree on 31st december 2002.
* Majors:VLSI Design(digital),VLSI Architecture, Analog VLSI Design, Physical Modeling of Microelectronic Devices,Integrated Electronic
System Design,CAD for VLSI design as part of the curriculum, in addition to other required
courses, as part of the curriculum.
* Current CGPA : 7.51

1998 - 2001
Bachelor of Science - Electronics & Communication Engineering
SRKR Engineering College,Bhimavaram, India
* Awarded Bachelor's Degree in Electronics and Communication Engineering from SRKR Engineering College,an affiliate of Andhra University, India.
Andhra University is in the Top 20 Universities in India. Graduated from the university with honors.
* Majors:Electronic Devices and Circuits, Digital Electronics, Digital Communication, Digital Signal Processing & Filter Design,Network Theory
in addition to other required courses.
* Percentage: 72.41

1993 - 1996
Diploma in Electronics and Communications Engineering.
AANM & VVRSR Polytechnic,Gudlavalleru, India
* Graduated with distinction and obtained a diploma in pre-engineering program.
* Percentage : 79.15
TECHNICAL SKILLS

Languages: VHDL, VERILOG, C, C++, FORTRAN-77, Assembly (8085), Pascal
Tools: Modelsim, FPGA Advantage, CADENCE NC-Simulator (Version 3.40) , Debussy, Tanner Tools(T-Spice, L-Edit, S-Edit,LVS),Wave Writer/AWE(Version 4.01e)
Operating Systems: Windows 2000/NT 4.0, Windows 98/95, Sun O/S, UNIX SVR 4.0

WORK EXPERIENCE/PROJECTS
Jun 2002 - Present Infineon Technologies Ag, Munich, Germany
Project Trainee/Intern

* Currently working as an intern at Infineon Technologies AG, Munich. Selected for internship after a thorough evaluation (through written tests
and interviews). This internship lasts until 31st December 2002.Responsibilities include Verilog coding for generation of test patterns and verification of Ethernet chip(Presilicon System Verification of an Ethernet Transceiver in 0.13um Technology).
This internship is the mandatory part of my Masters program.

Jan 2002 - May 2002 Birla Institute of Technology & Science
Implementation of Asynchronous Communication Interface Adapter (ACIA) in VHDL
* Asynchronous Communication Interface Adapter provides the data formatting and control to interface serial asynchronous data communications information to bus organized systems such as the MC6800 icroprocessor Units.The bus interface includes select, enable, read/write, interrupt and bus interface logic to
allow data transfer over an 8-bit bi-directional data bus.The parallel data of the bus system is serially transmitted and received by the asynchronous data interface, with proper formatting and error checking. The functional configuration of ACIA is programmed via the data bus during system initialization. A programmable Control Register provides variable word lengths, clock division ratios, transmit control,
receive control, and interrupt control. For peripheral or modem operation, three control lines are provided: Clear-to-send (CTS'), Request-to-send (RTS'),
Data-carrier-detect (DCD')

Jan 2002 - May 2002 Birla Institute of Technology & Science
Optimization of VHDL codes for event driven simulations
* This is a study project as a part of the course Computer Aided Design for VLSI Design. In this project the event driven VHDL simulations are optimized by making the simulation sensitive to the events, which will affect the output and internal signals as simulation advances. With this method we can reduce the simulation time, by avoiding the redundancy in execution that is caused by 'insensitive events'.Both
sequential and combinational circuits are considered for optimization.

Jan 2002 - May 2002 Birla Institute of Technology & Science
Low-Voltage Low-Power Wide-Range CMOS Variable Gain Amplifier
* This amplifier based CMOS transistors operating in strong inversion is composed of a multiplier, a pseudo-exponential current-to-voltage converter, and an output stage. A novel wide range pseudo-exponential current to voltage converter implemented with two back to back connected current mirrors exhibiting superb exponential characteristic controls the gain of amplifier exponentially. A new composite transistor
is introduced to increase the dynamic range of multiplier by adjusting the effective threshold voltage of each composite transistor.This is more suitable for Mixed Mode Integrated Circuit design to isolate the analog circuits from high noise nvironment of digital circuits.

Jun 2001 - Dec 2001 Birla Institute of Technology & Science
Implementation of LightfootTM JAVA Processor Core Using VHDL
* The 32-bit Lightfoot processor operates from a tiny memory footprint, providing an ideal design solution for embedded system OEMs. The memory referenced by programs falls into two categories: Program Memory and Data Memory. Program memory is 8-bit wide and is used to store program instructions and constant data. Data memory is 32-bit wide and is byte addressable. Words (32-bit wide) must be word aligned, half-words (16-bit wide) must be half word aligned. The key blocks of core, the Control Unit, ALU, Data and Return Stacks, CPU and Parameter Register.

Jun 2001 - Dec 2001 Birla Institute of Technology & Science
Standard Cell Design
* Negative edge triggered D Flip-flop with active low clear was done using 2 micron (mosis) technology with cell height of 50 microns. The delay after simulation is 1.71 ns. This project is done for standard cell library with 50 microns height.

Aug 2000 - Apr 2001 SRKR Engineering College
Image recognition by affine invariant descriptors
* This project studies the performance of various invariant pattern recognition techniques. The algorithms implemented are capable of recognizing the image even under affine transformations, which include rotation, translation and scaling. The descriptors implemented and tested in this project are Fourier Descriptors and Moment Invariants. A new parameter has
been proposed and also tested for affine invariance. This project is restricted to recognition
of alphabets, though the invariant can function for 2-D images. These algorithms have been implemented in turbo C++, and input can either be given through a scanner or through a programmed grid.

* PERSONAL INFORMATION
Sex: Male
Date of Birth: 16th March,1978
Marital Status: Single
Nationality: INDIAN

STRENGTHS
Hard Work, Good Team Member , Creativity

REFERENCES
References can be provided upon request.

OTHER INFORMATION
Work Sponsorship Required