Posted by on August 05, 19103 at 22:23:32:

Curriculum Vitae

HCL Technologies Ltd.,
N.V.Sreenivasa Reddy No.184,NSK Road,
Cell No: 9840241697 Vadapalni,
Email : namalareddy@yahoo.com Chennai, India
:
Bachelor of Engineering ( Electronics & Communication)

Educational Details:
Bachelor of Engineering ( Electronics & communication)
College : JNTU College Of Engg., Anantapur.
University : JNT University, Hyderabad.
Result : 78% (Aggregate)

Intermediate
Board Of Intermediate Education,
Result : 82%

S.S.C
Board Of Secondary Education,
Result : 80%

Professional Experience :
Experience : 4.0 years (nearly)

1. Designation : Member Technical Staff(MTS)
Period : Feb 2002 – till date
Organisation : HCL Technologies Ltd., Chennai

2. Designation : Design Engineer
Period : June 2002 – Feb 2002
Organisation : TeleCruz Technology Inc.,
Hyderabad.

3. Designation : Asic Engineer
Period : Oct 1999 – June 2002
Organisation : QualCore Logic (P) Ltd., Hyderabad.

Technical Skills :
Operating Systems : UNIX, Sun Solaris 5.7,
Windows 98

Languages
Hard Ware Description : Verilog
Programming : C, PLI
Scripting : AWK, Perl, C-Shell

Tools
HDL Simulator : Cadence Verilog-XL,Verilog-NC
Synthesis : Synopsys Design Compiler
Static Timing Analysis : Synopsys Design Compiler
Formal Verification : Synopsys Formality
DFT : Synopsys DFT Compiler
Other tools : Code coverage and lint tools
( surecov & surelint )

Projects Undertaken :

2. Integrated Interactive TV Controller:

Client : Sony,Panasonic,Videocon(India),Hi-Sense(China)
Team Size : 20
Gate Count : 2.8 M

Enables the End User to access the web using TV in addition to viewing
the television channels. The chip being inside the TV it allows user to
view the television channels and browse the web simultaneously.
Supports NTSC/PAL standards, progressive/interlaced scan, picture in
picture, closed captioning, and LCD TV.

Responsibilities:
Designing CRTC controller for multiple graphics/video surfaces
Design & Verification of 16-bit Stereo Audio Bus Master
Developed Boot & Audio test vectors using Verilog, C & gmake

3. MultiStream HDLC Processor:

Client : Virata Global ( UK, Israel )
Team Size : 10
Gate Count : 1.2 M

This macrocell implements logic required for interfacing with
bi-directional communication links,for processing data in HDLC
format,supports 256 different HDLC/transparent streams with
necessary temporary storage buffer and for the bi-directional
transfer of data through AHB. Essentially this block performs
the HDLC processing on packets at layer 2 of the ISO/OSI model.
Supports communication links with data in anyone of the formats
namely, T1/E1,2E1,4E1,192-bit T1,MVIP,H-MVIP,GCI,PEB,SCSA-Bus.
Supports streams occupying 8 or 7 or 2 or 1-bit of a timeslot.
Being a configurable core it supports 2links,64 streams in one
configuration and 4links,256 streams,ss7-mode in another.

Responsibilities:
Designing & RTL Coding using Verilog.
Synthesizing design using Synopsys DC
Static Timing analysis using DC(synopsys)
Verification of Rx stream processor block

4. standalone multichannel HDLC communication controller:

Client : Zilog
Team Size : 15
Gate Count : 1.5 M

This macrocell implements the logic required for interfacing
with 8 bi-directional communication links, for processing data
in HDLC format, for accommodating 256 different HDLC channels
with necessary temporary storage buffer and for the bi-directional
transfer of data to the PCI system memory. Framed data communication
links are supported through this block, it can handle HDLC channels
in different channelized formats T1, E1, 2T1/E1, 4T1/E1, MVIP format,
Unchannelized HDLC data in both transmit and receive directions is
supported. It also supports transparent(non-HDLC) framed data, in
channelized and unchannelized modes. Essentially this block performs
the HDLC processing on packets at layer 2 of the ISO/OSI model.

Responsibilities:
Creating system level test environment using Verilog, C, using PLI.

5. AMBA AHB Bus Master:

AHB is a high-performance on-chip system bus that supports multiple bus
masters and provides high bandwidth operation..

Responsibilities:
Development of AHB Bus Master model using Verilog.

Personal Performa:

Father's Name : N.Sanjeeva Reddy
Date of Birth : 01-07-1976

References : Available on request