Posted by on August 05, 19103 at 22:20:19:

Curriculum Vitae

HCL Technologies Ltd.,
N.V.Sreenivasa Reddy No.184,NSK Road,
Cell No: 9840241697 Vadapalni,
Email : namalareddy@yahoo.com Chennai, India

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Objective:
To pursue a challenging career in ASIC design and
development.

Qualification:
Bachelor of Engineering ( Electronics & Communication)
JNTU College Of Engg., Anatapur,
JNT University,Hyderabad.
India

Educational Details:
Bachelor of Engineering ( Electronics & communication)
College : JNTU College Of Engg., Anantapur.
University : JNT University, Hyderabad.
Result : 78% (Aggregate)

Intermediate
Board Of Intermediate Education,
Result : 82%

S.S.C
Board Of Secondary Education,
Result : 80%

Professional Experience :
Experience : 4.0 years (nearly)

1. Designation : Member Technical Staff(MTS)
Period : Feb 2002 – till date
Organisation : HCL Technologies Ltd., Chennai

2. Designation : Design Engineer
Period : June 2002 – Feb 2002
Organisation : TeleCruz Technology Inc.,
Hyderabad.

3. Designation : Asic Engineer
Period : Oct 1999 – June 2002
Organisation : QualCore Logic (P) Ltd., Hyderabad.

Technical Skills :
Operating Systems : UNIX, Sun Solaris 5.7,
Windows 98

Languages
Hard Ware Description : Verilog
Programming : C, PLI
Scripting : AWK, Perl, C-Shell

Tools
HDL Simulator : Cadence Verilog-XL,Verilog-NC
Synthesis : Synopsys Design Compiler
Static Timing Analysis : Synopsys Design Compiler
Formal Verification : Synopsys Formality
DFT : Synopsys DFT Compiler
Other tools : Code coverage and lint tools
( surecov & surelint )

Projects Undertaken :

2. Integrated Interactive TV Controller:

Client : Sony,Panasonic,Videocon(India),Hi-Sense(China)
Team Size : 20
Gate Count : 2.8 M

Enables the End User to access the web using TV in addition to viewing
the television channels. The chip being inside the TV it allows user to
view the television channels and browse the web simultaneously.
Supports NTSC/PAL standards, progressive/interlaced scan, picture in
picture, closed captioning, and LCD TV.

Responsibilities:
Designing CRTC controller for multiple graphics/video surfaces
Design & Verification of 16-bit Stereo Audio Bus Master
Developed Boot & Audio test vectors using Verilog, C & gmake