Posted by on July 24, 19103 at 15:53:41:

PERSONAL PROFILE :

NAME : Prashant Maruti Sahane
ADDRESS : AL-1/353, Sector-16,
Airoli, Navi Mumbai - 400708.
DATE OF BIRTH : 11th Aug 1977.
PHONE NO. : (022) 2760 1427.
MOBILE NO. : 9820516516
EMAIL : prashantsahane@yahoo.com
prashantsahane@hotmail.com

EDUCATION : B.E. Electronics Aug 1999, PUNE, INDIA
Diploma in Industrial Electronics, INDIA

EXPERIENCE : Total Experience 3+ years in Data Communications,
and Microprocessor based System design and Digital Designs.
Have Expert knowledge in USB, Gigabit Ethernet MAC, and good
knowledge on SONET.

Worked on Assertion Based Verification using Open Vera Assertions (OVA). Developed Open Vera Assertions based USB2.0 Function Controller Checker IP.

Knowledge in all aspects of Design Life Cycle through Specification, Design Engineering, Modeling, Integration, Verification, Documentation, including Code Documentation and Maintenance.

SKILLS( EDA Tools/Languages)

Computer System : Intel-based Pentium
Operating System : Microsoft Windows 95, 98, NT/2000, Linux
Modeling Languages : VHDL, Verilog HDL, Vera HVL, Perl, OVA,
C Language
Assembly Languages : 8085, 8086, 8051
Development Tools : Model Technology ModelSim 5.7 / SE (Mentor
Graphics), Wellspring Solutions Veriwell, Xilinx Foundation Series FPGA Development System, Leonardo Spectrum from Exemplar Logic, Synopsys VCSi, Vera and OVA tool

Additional Qualification :

Completed Certificate course in advance German with ‘A’ Grade.

EMPLOYMENT HISTORY :

April’ 2001 Till date :
SILICON INTERFACES (I) PVT LTD, SEEPZ, MUMBAI
as Assistant Engineer, VLSI
Dec’1999 to June’2000 :
COMPUTR FACTORY (I) PVT LTD, THANE
as an Electronics Engineer.

Training :

1.Undertaken 4-days training on OVA Language and Development of OVA based checker IP.

2. Full 3-days training on Introduction to Vera tool and Open Vera Language from Synopsys’s Customer Education Services. Training includes writing an effective Testbench for HDL Design using VERA.

3. Undertaken six months training program in Pune Institute of
Advance Technology (PIAT), India on Design and development of digital
systems using VHDL / Verilog.
Duration : Aug 2000 to Feb 2001.

Industrial Experience and Projects:

#1. USB2.0 Function Controller OVA Checker IP
Site : Silicon Interfaces, India
Team size : 3
Platforms : Intel Pentium III.
Operating Systems : Linux
Development Language : OVA (Open Vera Assertion)
Design Tools : Synopsys VCSi7.0

Description: USB2.0 openvera assertion based VIP provides a concise declarative mechanism to code the specification of sequences of events & activities of USB2.0 Bus Protocol. USB2.0 ova protocol rule checker can work in a standalone mode i.e. can be plugged in any design verification enviournment, which uses the standard Protocol without disturbing the structure. USB2.0 ova checker is developed using the abstraction in OVA syntax that is used in dynamic simulation of USB2.0 based design.

My Contribution: Involved in the checker list preparation of the USB2.0 specifications. Implementation of the checker list in OVA.

#2. SI16USB20 Function Controller core
Site : Silicon Interfaces, India
Team size : 3
Platforms : Intel Pentium III.
Operating Systems : Microsoft Windows NT/2000, Linux Development Languages : Verilog HDL
Design Tools : Model Sim 5.5, Exemplar Leonardo
Spectrum, Xilinx FPGA Foundation series

Description :
This core provides USB high-speed function interface that meets USB2.0 standards. The logic handles the data transfer, buffering and bridges the USB interface to simple read/write parallel interface. The core can be customized and optimized for a specific application. The functional blocks are Protocol Layer, UTMI interface, Data buffer, Microcontroller Interface.

My Contribution :
Designing of Protocol Engine block. This consists of packet assembly, dis-assembly, transaction controller and endpoints implementation. Verilog coding of these modules and functional verification. The protocol engine block handles all transactions as per USB2.0 specifications.

#3. SI50GE22 - Gigabit Ethernet Controller core
Site : Silicon Interfaces, India
Team size : 4
Platforms : Intel Pentium III.
Operating Systems : Microsoft Windows NT/2000, Linux
Development Languages : Verilog HDL, Vera
Design Tools : Synopsys VCSi, Model Sim 5.5,
Vera tool, Leonardo Spectrum.

Description:
The Gigabit Ethernet Controller core consists of Transmitter, Transmit FIFO Receiver block, Receive FIFO, Flow control and a generic Host interface block which can be easily adopted for required host interface. The core can be used in various integrated applications with Gigabit baud rate for media access control.

My Contribution:
Detailed study of Ethernet Controller. Designing and coding the Flow Control block, consisting of sub modules. These modules include Pause Timer, Pause Frame Generator, Pause FIFO, counters, data path. Functional Verification of individual modules and Transmitter block.

#4. Cache Memory System ( Write Back Cache)
Site : Silicon Interfaces, India
Team Size : 3
Platform : Intel Based Pentium.
Operating System : Microsoft Windows NT
Development Language : Verilog HDL
Design Tools : Model Sim 5.4A.

Description :
Development of a Cache Memory System (Write back Cache) from
Data Sheet to structural code. It incorporates look through read
architecture and direct mapped technique with a dedicated controller.
Designed Modules include: Tag Ram, Data Ram, Valid Bits Ram, Tag
Comparator, Data Multiplexer, control Section FSM, Data Flow
Architecture.

My Contribution :
Modified the control Section Finite State Machine of the
cache , so as to implement write back and look through read architecture efficiently.

#5. Memory Controller.
Site : PIAT Pune, India
Team Size : 4
Platform : Intel based Pentium.
Operating System : Microsoft Windows NT
Development Language : VHDL HDL
Design Tools : Model Sim PE/PLUS.

Description :
The Design of memory controller was done with the specifications similar to PCI specifications. That is the read and write cycles are implemented according to the PCI specifications. It has Byte Enable, Frame, Trdy, Irdy etc. Similar to PCI.

My Contribution :
Designed the Finite State Machine of the memory controller. Tested the
functionality using the testbench written in VHDL.