Posted by on July 07, 19103 at 05:43:12:

Qazi Faheem Ahmed
HOUSE NO. 255(A)/1, ZAKIR NAGAR NEW DELHI-110025, INDIA
PHONE +91-011-26988545
E-MAIL: QAZIFAHEEMAHMED@YAHOO.COM

OBJECTIVE
To excel in the field of VLSI design, development, implementation and applications. Specific areas of interest include design and FPGA implementation of DSP algorithms such as Image Compression, Vector Quantization and Video Compression.
ACADEMIC BACKGROUND
Pursuing B-Tech (final year) in Electrical Engineering from Faculty of Engineering & Technology, Jamia Millia Islamia, New Delhi.
B-Tech Expecting 65% as aggregate of all four years
S.S.E 63%
Matriculation 73.65%
CURRENT PROJECTS
September 30th –28th June
VLSI implementation of Motion Estimator for MPEG Digital Video Coding Standard and Comparative Analysis of Block Matching Motion Estimation Techniques
A VLSI implementation of the Full Search Algorithm for Reconfigurable Motion Estimation has been done. A pipelined architecture has been devised. 256 processing elements and on chip memory has been used to increase the speed of operation. The Motion Estimator works on full pixel precision estimation over a search range of -16/+16 pixels or more, for each 16 x 16 or 8 x 8 block in a frame (CIF resolution, 352 x 288 or QCIF resolution, 176 x 144) at 30 fps. 4-1 or 2-1 pixel subsampling is also supported. A comparative analysis of Block Matching Motion Estimation Techniques is also a part of the project.
Team Size Four members
Role Algorithm Analysis, Design and Code Development
Platform Active HDL 5.1
HDL used Verilog
Tool used Xilinx WPx.1
Operating System Windows-98

July 20th –Till Date
Digital Testing of ASICS and E-beam Probing , under Dr. K.S. Chari, Director, Dept. of Electronics, Ministry of Information Technology, Govt. of India
Project Description
a) Digital Testing of ASICs: Includes design for testability (DFT), Built-in self test (BIST), test pattern calculation (TPC) and Measurement Techniques.
b) E-Beam Probing: Includes comparison of other scanning methods with E-beam probing, study of E-beam prober (Techniques and Technology) and Scanning Electron Microscopy.
c) Interfacing: Interfacing the E-beam prober to other devices, like ASIC tester, interfacing requirements, methods, direct docking of ASICs.
Team Size Six members
Role Interfacing

RESEARCH
1. Award winning Paper in a national level technical symposium titled “VLSI architecture for Hybrid DCT-SVD image coding algorithm”, also selected for presentation and publication at the International Signal Processing Conference, held at Dallas, Texas, from March 31st to April 4th, 2003, after slight modification/improvement.
The paper is based on a hybrid transform scheme of image compression, involving the discrete cosine transform and the singular value decomposition. The transform used depends upon the nature of the frequency components of the image. High frequency components are transformed using SVD and low frequency components using DCT. The choice of transform to be used is evaluated by calculating the variance of an 8x8 block. If the variance is higher than a specified threshold, SVD is used. Considerable improvement of picture quality is achieved at slight expense of compression ratio. A pipelined architecture for 2D-DCT and microcontroller based architecture for variance calculation was proposed. Already available systolic architecture was assumed for SVD.
2. Case Study and Presentation of MPEG Video Compression Standard
A case study of MPEG Video Compression was done. Various parts of the MPEG algorithm were studied in detail, including JPEG image compression algorithm. In addition, MPEG encoder/decoder was studied from the H/W implementation point of view. The case study was presented in the Faculty of Engineering & Technology, Jamia Millia Islamia.

COMPUTER KNOWLEDGE

High Level Languages
C, Pascal
Low Level Languages
8085 Assembly
HDLs
VHDL, Verilog-HDL
Operating Systems
Sun Solaris, Unix, Windows 9x/2000/XP, DOS
CAD Tools
MATLAB 6.1, Xilinx WPx.1 series tools
TRAINING
August 31st – December 28th , 2002

Underwent training at C-DAC (Formerly ER&DCI), NOIDA in VHDL and Verilog modeling.

HDLs Verilog and VHDL
Tools Cadence Design Tools
Operating System Sun Solaris
SUBJECTS OF INTEREST
VLSI, Microprocessor, Digital Electronics, Computer Architecture, Analog Electronics, Digital Signal Processing, Computer Networking, Image and Video Processing, Communication Systems
LANGUAGES KNOWN
English, Urdu, Hindi
EXTRACURRICULAR ACTIVITIES
Organized the University Cultural Festival held in November 2002 as the President of the cultural activities forum of the Faculty of Engineering & Technology.
Active student member of the IEEE
HOBBIES
Playing Electric Guitar, Reading News Articles, Community Service