Posted by on June 17, 19103 at 20:21:41:

T.D. MANOJ KUMAR REDDY
192,1st floor,adarsh complex, N.R.layout,
Garvebhavi playa,Hosur Road,Bangalore-68
Ph: 51119537 e-mail : tdmanoj@rediffmail.com, manoj_td@yahoo.com

Career Objective :
To achieve efficiency and a challenging position in VLSI and Embedded systems,development with the state of art technology where my analytical skills and creativity can be put in for successful completion of project.

Educational Qualifications : -B.E.(ECE) from SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY Affiliated to BANGALORE University in MAR-2001.

TECHNICAL SKILLS :-
Operating Systems : MS-DOS ,Windows 95/98
Low level Programming Languages : 8085,8086
High level Programming Languages : c,c++
Hardware Descriptive Languages : VHDL
Software Tools : Altera-Max-Plus-II, Or cad, p-spice.

PERSONAL PROFILE:-
Date of Birth : 18 APR 1978
Permanent address : s/o T.D.Mohan Reddy,gandodivari palli(post),
Tanakal (mandal),Ananthapur(Dt)
Andra pradesh 515571.Ph:08498-252074
Nationality : Indian
Sex : Male
Languages Known : English, Hindi, Telugu, and Kannada.

EXPERIENCE SUMMARY:- Working as Design &Testing Engineer in S.V.TECHNOLOGIES under
Ex- scientist of NRSA , since june2001 in Hyderabad.

RESPONSIBILITIES:- R& D of required logic and testing in ECL and TTL mode, Implementing the desired logic Using ALTERA- MAX-PLUS II Software, programming it on EPLD’S test on the PCB and writing technical documentation.
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PROJECTS HANDELED:-

Title of the project:1
Title :“Clock Recovery And Synchronization Of Digital Data Communication System”
Team size : Four
Technology used : VLSI-EPLD’S(TTL)-EPM7032ALC44-4
Duration : 4 months
Organization : L.R.D.E, Bangalore
Role in the project : Design of all the circuits in TTL mode and enter the circuits in ALTERA-MAXPLUS –II SOFTWARE by graphical entry(VHDL)and testing the all the circuits in wave form file by giving input and output .After testing in soft ware, all the files are program on the EPLD’S. testing the circuits live on PCBs.

Project discription:- The project is used to recover the clock from the transmitted data and synchronization of received digital data. The circuits in the project as follows.
Clock Recovery: - The receiver requires proper clock information to decode the received data without error. The clock recovery circuit is used to recover the clock information from the received data stream.
Synchronization: It is required to recognize the start and end of each frame to separate the various fields from frame. The synchronization circuitry uses the sync bit format to achieve synchronization. A suitable algorithm should be devised to achieve synchronization even in the presence of imitation.
Field combination : - The frame consists of three parts they are, 8-bit synchronization slot,8-bit control signal slot & 16-bit data slot. All these bits are generated by different sections but before frame transmission all these bits have to be grouped together to form a single frame.

Title of the project:2
“BIT ERROR RATE SYSTEM (BER)” (For 90 Mhz input clock using Discrete circuits)
Team size : Two
Client : ISRO, Bangalore
Technology used : Digital ECL circuits
Period of project : 7 months
Role in the project : Design of prescaler, ratio counter and switching circuits, draw the circuits on ORCAD soft ware, checking the films and PCBS and testing the circuits live on PCBs using testing equipments , and writing technical documentation.
Testing equipments used : Oscilloscope, Gigatronics clock source, crystal oscillators
BNC-BNC,BNC-SMA cables, adapters, ECL IC’s,+5v,-5v,+15v power supplies, ,LED,LCD, DATEL frequency display, keypad,4u mechanical box,.

Title of the project:3
BIT ERROR RATE SYSTEM (BER) (For 110Mhz Clock Using EPLD’S)
Team size : Two
Client : DIPAC, Delhi
Technology used : VLSI-EPLD’S(TTL)-EPM3032ALC44-4
Software used : Altera max-plus-ii
Duration of project : 5 months.
Role in the project : Design of all the circuits in TTL mode and enter the circuits in ALTERA-MAXPLUS –II SOFTWARE by graphical entry(VHDL)and testing the all the circuits in wave form file by giving input and output .After testing in soft ware, all the files are program on the EPLD’S. Draw the circuits pin configurations and placements using ORCAD soft ware, checking the films and PCBs and testing the circuits live on PCBs using testing equipments, and writing technical documentation
Testing equipments used : Oscilloscope, Gigatronics clock source, crystal oscillators
BNC-BNC,BNC-SMA cables, adapters, ECL IC’s,+5v,-5v,+15v ,+3.3vpower supplies, ,LED,LCD, DATEL frequency display, keypad,3u mechanical box,.
Description of the project : The project consisting of two sections Transmitter and Receiver. BER equipment detects the data from the transmitter is read by receiver correctly or not. If it read correctly
The error is zero other wise it read the errors. some of the circuits description is as follows.
TRANSMETER END :- It consisting of following circuits
Data Generator : It generates pseudo random data of 10^15–1 and 10^23 –1 code lengths from i/p clock.
Encoder : It encodes the data in phase and quarter phase of desired algorithm to the receiver end.

RECEIVER END :- It consisting of following circuits
Decoder: It decodes the data in phase and quarter phase of desired algorithm from the transmitter end.
Error Detector: It to read the errors in data received for 10^15 –1 and 10^23 –1 code lengths.
Prescaler circuit: It prescale the clock for displaying the clock on the frequency counter.
Ratio counter and switching: It is used for display the errors and exponent on LED display.
Keypad &LCD Display: Selections are selected from the keypad and displayed on LCD display using GPIB/IEEE interface.Controls are given from the keypad using GPIB circuits(local ode). controls also given from the IEEE interface(remote) from the computer .

I certify that the information I have provided is correct and I shall be wholly responsible if any information is provided to be fake.

Place: Bangalore
Date: (T.D. Manoj Kumar Reddy.)