Posted by on June 05, 19103 at 12:20:28:

SUNIL KATASANI
©602-690-5786

Summary:

Five (5) years of strong experience in design, verification and implementation of High speed ASIC and FPGA circuits and systems. Strong skills in designing at RTL, behavioral, architectural and board level test. Exclusive experience in VHDL, Verilog synthesis and simulation environments of major EDA vendors.

Tools / Skills:

Hardware Description Languages: VHDL, Verilog
Scripting Languages: Perl, Tcl/Tk
Languages: C, C++
Verification: PLI
Operating Systems: Sun Solaris, Linux, Windows NT/2000
Simulation Tools: Cadence’s NC Simulator, Synopsys VSS and VCS Simulator, Mentor Graphics Modelsim
Synthesis Tools: Synopsys’s Design Compiler & Design Analyzer
Timing Analyzers: Synopsys PrimeTime
FPGA Tools: Altera’s Max+plus II, Xilinx Foundation Series, Xilinx ISE, Synopsys FPGA Express, Aldec's Active-VHDL, Synplicity's Synplify
PCB Design : Orcad
Test Equipment: HP Oscilloscopes, HP & FastBit Bit Error Analyzers, HP
Logic Analyzers, Logic Probes

Experience:

Encamera Sciences Corp., Scottsdale, AZ. June 2001 to Till Date
Sr. Digital Design Engineer

802.11b MAC
Designed and developed MAC layer for 802.11b wireless LAN. Coded RTL and used ModelSim for functional & gate level simulation, Synopsys Design Compiler for synthesis. Used PLI and C for functional verification of the MAC.

Environment: Verilog, ModelSim, Synopsys DC.

FEC for Data Over Television
Designed and developed Forward Error Correction module (Encoder/Decoder) used for transmitting and receiving data over television at 1.5 Mbps with PCI add-on card. Used AHA 4524 (turbo product code encoder/decoder) for encoding and decoding. Used analog devices AD9850 direct digital synthesizer for payload clock generation at the transmitting and receiving ends. Designed an interface for configuring the AD9850 for different code rates of AHA 4524.Targeted the design into a Virtex-II FPGA XC2V1000-FG256-4. Converted the design from VHDL to Verilog for integration with other modules. Coded RTL and used ModelSim for functional & gate level simulation, Synplicity’s Synplify for synthesis and Xilinx Foundation ISE for place & route. Used Orcad for board design.

Environment: VHDL, Verilog, ModelSim, Synplify, Xilinx Foundation ISE, Windows 2000.

U & I Scotty Computers Limited, India. August 00 to May 01
ASIC Design Engineer

Serial EEPROM Interface
Designed and developed an EEPROM interface to provide an interface to industry standard serial EEPROM using VHDL. The 24C00 technology provided 1024 bits of serial EEPROM organized as 128 words of 8 bit each. Designed two-wire interface for 24C00 used to store device ID and other configuration information of the chip. Coded RTL and used Cadence’s NC Simulator for functional simulation, Synopsys Design Compiler & Design Analyzer for synthesis and Synopsys VSS Simulator for gate level simulation.

Environment: VHDL, Cadence’s NC Simulator, Synopsys’s VSS Simulator and Design Compiler, Design Analyzer, Sun Solaris 5.7.

SDRAM Controller
Designed a SDRAM Controller to provide a simple interface to industry standard SDRAM, Used VHDL to design SDRAM controller to use it with MPEG core since it needed a frame memory for encoding and decoding streams. Developed SDRAM controller to support burst and page mode. Coded RTL and used Cadence’s NC Simulator for functional simulation, synopsys design compiler & design analyzer for synthesis and synopsys vss simulator for gate level simulation.

Environment: VHDL, Cadence’s NC Simulator, Synopsys VSS Simulator, Design Compiler, Design Analyzer Sun Solaris 5.7

USB 1.1 Device Controller
Designed an USB 1.1 device controller. Used VHDL to design the device controller. Coded RTL and used Cadence’s NC Simulator for functional simulation, synopsys design compiler & design analyzer for synthesis and synopsys vss simulator for gate level simulation.

PARK Controls & Communications Limited, India. March 98 to July 00
Design Engineer

Link Layer Support Chip
Designed and developed PCI module for PCI add-on card for 1394 node. Designed PCI Master using Verilog HDL.Used Synplicity’s Synplify for synthesis and Xilinx Foundation Series for place and route. Targeted the design into a Virtex FPGA XCV600-HQ240-6. Coded RTL and used Modelsim for functional and gate level simulation.

Environment: Verilog HDL, Xilinx Foundation Series, Synplicity Synplify, Modelsim, Virtex FPGA, Windows NT

Data Interface Unit with Golay Encoder Decoder
Designed and developed data interface unit (DIU) using VHDL with Xilinx Foundation series software to connect personal computers or any other equipment with RS-232 to radio trans-receivers and facilitate data transfers over radio link. Used Golay code for encoding, decoding and immunize signal from noise errors as it has a correcting capability upto three bit errors. Organized transmitted data as 12-bit blocks and encoded each block into 23-bit code word. Thirty-six such code words are interleaved and sent as block. 64-bits of unique programmable sync pattern is used for block separation. Sent 8 blocks as one frame of data. Used correlator (for sync detection), de-interleaver (to decode received frame) and syndrome generator (to compute the error pattern) at receiving end. Implemented DIU in Xilinx XCS40-3-PQ-208 FPGA and XC-95144-PQ-160 CPLD for initializing FPGA. Coded RTL and used Aldec’s Active VHDL for functional and gate level simulation.

Environment: VHDL, Xilinx Foundation Series, Aldec’s Active VHDL, RS-232, Windows NT

Programmable Timer
Designed and implemented a countdown timer in Altera EPM-7128E EPLD for missile launch control center. Designed a standalone timer to give Binary Coded Decimal timeout to launch control center (LCC). Coded RTL and used Active VHDL for functional and gate-level simulation. LCC, a vehicle based computer center connected to launcher kept at a safe distance to connect pre-launch mission sequence for a successful takeoff.

Environment: VHDL, Altera’s Max+plus II, Windows NT.

Education:

MS in Electrical Engineering.